2010年度

  • 学会誌

    飯田全広，末吉敏則
    ``FPGA/CPLDの変遷と最新動向[III]─FPGA向け設計ツール─，''
    信学誌，vol.93，no.8，pp.711-716，Aug. 2010.

    末吉敏則，久我守弘
    ``FPGA/CPLDの変遷と最新動向[IV] ─FPGAとリコンフィギュラブルシステム─，''
    信学誌，vol.93，no.9，pp.809-815，Sep. 2010.

    末吉敏則，尼崎太樹
    ``FPGA/CPLDの変遷と最新動向[V・完]─FPGA と特許─，''
    信学誌，vol.93，no.10，pp.873-879，Oct. 2010.

  • 論文誌

    Shunsuke Oshima, Takuo Nakashima and Toshinori Sueyoshi
    "Extraction of Anomary Accessed IP Packets Features using Statistical Method",
    International Journal of Innovative Computing, Information and Control(IJICIC), Vol.6, No.8, pp.3725-3735 ,Aug. 2010

    Kazuki Inoue, Zhao Qian, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi,
    ``A Variable Grain Logic Cell and Routing Architecture for Reconfigurable IP Core",
    ACM Trans. Reconfig. Techn. Syst, 4.1, Article 5, 24 pages, DOI 10.1145/1857927.1857932. Dec. 2010

    小島俊輔, 中嶋卓雄, 末吉敏則
    ``エントロピーベースのマハラノビス距離による高速な異常検知手法，''
    情報処理学会論文誌, Vol.52, No.2, pp.656-668, Feb. 2011

  • 国際会議

    Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi,
    ``Improving the Robustness ofs a Softcore Processor against SEUs by using TMR and Partial Reconfiguration,''
    Proc. the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2010), pp.47-54, Charlotte, North Carolina, USA, May 2010.(2010/5/3発表)

    Y.Sato, M.Koga, M.Amagasaki, M.Iida and T.Sueyoshi
    ``Development of power estimation tool for Variable Grain Logic Cell,''
    Proc. the 4th International Student Conference on Advanced Science and Technology(ICAST), pp207-208, Izmir, Turk, May 2010. (2010/5/25発表)

    K.Yoshizawa, K.Inoue, Y.Okamoto, Q.Zhao, H.Yosho, M.Koga, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
    ``Design of Prototype Chip Based on Variable Grain Logic Cell Architecture,''
    Proc. the 4th International Student Conference on Advanced Science and Technology(ICAST), pp213-214, Izmir, Turk, May 2010. (2010/5/25発表)

    H.Yosho, M.Koga, M.Amagasaki, M.Iida and T.Sueyoshi
    ``A case study of efficient test circuits for Reconfigurable Logic Devices,''
    Proc. the 4th International Student Conference on Advanced Science and Technology(ICAST), pp215-216, Izmir, Turk, May 2010. (2010/5/25発表)

    Y.Ichinomiya, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi
    ``Improving the Reliability of FPGA system by using TMR and Partial Reconfiguration,''
    Proc. International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART), pp107-112, Tsukuba, Japan, June 2010. (2010/6/1発表)

    J.Eto, S.Nishida, M.Amagasaki, M.Iida and T.Sueyoshi
    ``Power-aware FPGA Routing Structure and Design Tools,''
    Proc. International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART), pp113-118, Tsukuba, Japan, June 2010. (2010/6/1発表)

    M.Koga, M.Iida, M.Amagasaki, Y.Ichida, M.Saji, J.Iida and T.Sueyoshi
    ``First Prototype of a Genuine Power-Gatable Recon" gurable Logic Chip with FeRAM Cells,''
    Proc. 20th International Conference on Field Programmable Logic and Applications (FPL2010), pp.298-303, Milano, Italy, Aug. 2010.(2010/9/1発表)

    Y.Okamoto, Y.Ichinomiya, M.Amagasaki, M.Iida and T.Sueyoshi
    ``COGRE:A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization,''
    Proc. 20th International Conference on Field Programmable Logic and Applications (FPL2010), pp.304-309, Milano, Italy, Aug. 2010.(2010/9/1発表)

    T.Kimura, N.Kai, M.Amagasak, M.Kuga and T.Sueyoshi
    ``A Case Study of Soft Error Emulation for SRAM-based FPGA Circuits,''
    Proc. 2010 Joint Conference of Electrical and Electronics Engineers in Kyusyu, 12-1A-05 , Fukuoka, Japan, Sep. 2010. (2010/9/25発表)

    H.Yosho, K.Inoue, M.Koga, M.Amagasaki, M.Iida and T.Sueyoshi
    ``A Test Scheme using Shift-based Configuration for Homogeneous FPGAs,''
    Proc. 2010 Joint Conference of Electrical and Electronics Engineers in Kyusyu, 12-1A-05 , Fukuoka, Japan, Sep. 2010. (2010/9/25発表)

    S.Nishida, J.Eto, Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi，
    ``Powe-aware FPGA Routing Fabrics and Design Tools,''
    Proc. the 18th IFIP International Conference on Very Large Scale Integration (VLSI-SoC2010), pp.67-72, Madrid, Spain, Sep. 2010.(2010/9/27発表)

    Y.Ichinomiya, Motoki Amagasaki, M.Kuga and Toshinori Sueyoshi，
    ``Soft-error Tolerability Analysis for Triplicated Circuit on an FPGA,''
    Proc. the 16th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI2010), pp.448-453, Taipei, Taiwan, Oct. 2010.(2010/10/19発表)

    Shunsuke Oshima, Takuo Nakashima and Toshinori Sueyoshi,
    "DDoS Detection Technique using Statistical Analysis to Generate Quick Response Time,"
    The Second International Workshop on Network Traffic Control, Analysis and Applications (NTCAA-2010), Fukuoka, Japan, Nov. 2010

    Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi，
    ``A Less Configuration Memory Reconfigurable Logic Device with Error Detect and Correct Circuit",
    Proc. of IEEE Region 10 International Technical Conference (TENCON2010), T6-2.2, Fukuoka, Japan, Nov. 2010(2010/11/22発表)

    Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Hiroki Yosho, Komei Yoshizawa, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi，
    ``A Prototype Chip of Reconfigurable Logic Device using Variable Grain Logic Cell Architecture",
    Proc. of IEEE Region 10 International Technical Conference (TENCON2010), T6-2.3, Fukuoka, Japan, Nov. 2010(2010/11/22発表)

    Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida and Toshinori Sueyoshi，
    ``A Power-Gatable Reconfigurable Logic Chip with FeRAM Cells",
    Proc. of IEEE Region 10 International Technical Conference (TENCON2010), T6-2.4, Fukuoka, Japan, Nov. 2010(2010/11/22発表)

    Tsuyoshi Kimura, Noritaka Kai, Motoki Amagasaki, Morihiro Kuga and Toshinori Sueyoshi，
    ``A Case Study of Evaluation Technique for Soft error Tolerance on SRAM-based FPGAs",
    Proc. of IEEE Region 10 International Technical Conference (TENCON2010), T6-2.5, Fukuoka, Japan, Nov. 2010(2010/11/22発表)

    Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi，
    ``A Robust Reconfigurable Logic Device Based on Less Configuration Memory Logic Cell",
    Proc. of International Conference on Field-Programmable Technology(ICFPT10), pp.162-169, Beijing, China, Dec. 2010(2010/12/9発表)

    Shunsuke Oshima, Takuo Nakashima and Toshinori Sueyoshi,
    "Anomaly Detection using Chi-Square Values based on the Typical Features and the Rime Deviation,"
    25th International Conference on Advaanced Information Networking and Applications (AINA2011), Singapore, Mar. 2011

  • 一般講演発表

    古賀正紘，飯田全広，尼崎太樹，市田善信，佐治満郎，飯田　淳，末吉敏則
    ``FeRAMを用いた不揮発リコンフィギャラブルロジックデバイスの試作，''
    信学技報 RECONF2010-5，vol.110，no.32，pp.25-30，May 2010. (2010/5/13発表)

    木村剛士，甲斐統貴，堤　喜章，尼崎太樹，久我守弘，末吉敏則
    ``SRAM型FPGA上の実装回路におけるソフトエラー耐性評価手法の一検討，''
    信学技報 RECONF2010-7，vol.110，no.32，pp.37-42，May 2010. (2010/5/13発表)

    小島俊輔, 中嶋卓雄, 末吉敏則
    “時間応答性を考慮したDDoSの統計的検出手法”,
    情報処理学会DPS研究会論文集, IEICE technical report 110(40), pp.41-48, May 2010

    朝永健司，久我守弘，末吉敏則
    ``変数の有効データ範囲を考慮したビット幅解析手法の検討，''
    若手の会セミナー2010講演論文集，情報処理学会九州支部，pp.29-33，Sep. 2010. (2010/9/11発表)

    堤 喜章，久我守弘，末吉敏則
    ``タスクの振舞いを考慮した動的再構成システム向けスケジューリングの検討，''
    若手の会セミナー2010講演論文集，情報処理学会九州支部，pp.35-40，Sep. 2010. (2010/9/11発表)

    岡本康裕，一ノ宮佳裕，尼崎太樹，飯田全広，末吉敏則 ``COGRE: 面積削減を目的とした少構成メモリ論理セルアーキテクチャ，''
    信学技報 RECONF2010-31，vol.110，no.204，pp.79-84，Sep. 2010. (2010/9/17発表)

    Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi
    ``An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device，''
    信学技報 RECONF2010-32，vol.110，no.204，pp.85-90，Sep. 2010. (2010/9/17発表)

    小島俊輔, 中嶋卓雄, 末吉敏則
    “代表的な特徴量と時間の揺れに基づいたχ二乗値による異常検知”,
    情報処理学会マルチメディア通信と分散処理ワークショップ論文集(DPSWS2010), pp.167-172, Oct. 2010

    堤 喜章，久我守弘，末吉敏則
    ``タスクの振舞いを考慮した動的再構成システム向けスケジューリングの検討，''
    信学技報 RECONF2010-43，vol.110，no.319，pp.25-30，Nov. 2010. (2010/11/30発表)

    朝永健司，久我守弘，末吉敏則
    ``高位合成を意識した変数の有効データ範囲解析手法の検討，''
    信学技報 CPSY2010-32，vol.110，no.318，pp.1-6，Nov. 2010. (2010/11/30発表)

    藪田敏生，一ノ宮佳裕，久我守弘，末吉敏則
    ``FPGAにおける高速シリアル通信を用いたASICエミュレータ向け配線仮想化の検討，''
    信学技報 CPSY2010-33，vol.110，no.318，pp.7-12，Nov. 2010. (2010/11/30発表)

    澤田拡臣，久我守弘，末吉敏則
    ``FPGAの配線処理におけるチャネル幅探索の分散並列化，''
    信学技報 CPSY2010-44，vol.110，no.361，pp.31-36，Jan. 2011. (2011/1/17発表)

    益満裕司，尼崎太樹，飯田全広，末吉敏則 ``クラスタベースFPGAにおける論理ブロック内のローカル配線最適化，''
    信学技報 RECONF2010-73，vol.110，no.362，pp.139-144，Jan. 2011. (2011/1/18発表)

    用正博紀，井上万輝，尼崎太樹，飯田全広，末吉敏則 ``スイッチブロックのトポロジに着目したFPGAの配線テスト手法，''
    信学技報 RECONF2010-74，vol.110，no.362，pp.145-150，Jan. 2011. (2011/1/18発表)

    吉澤孔明，井上万輝，尼崎太樹，飯田全広，末吉敏則 ``シフタ付きスイッチブロックを用いたFPGA配線構造の設計，''
    信学技報 CAS2010-88，vol.110，no.389，pp.23-28，Jan. 2011. (2011/1/25発表)

  • ポスター

    久我守弘，``システムLSI設計技術者育成のための演習教材開発（第2報），''
    平成22年度 工学・工業教育研究講演会講演論文集，P-11，pp.678-679， Aug. 2010. (2010/08/21発表)

    久我守弘，``ユビキタスネットワークを用いる情報収集・解析・制御実験の一提案，''
    平成22年度 工学・工業教育研究講演会講演論文集，P-12，pp.680-681， Aug. 2010. (2010/08/21発表)