2017年度

  • 論文誌

    M.Amagasaki, Y.Nishitani, Kazuki Inoue, Masato Iida, Morihiro Kuga and Toshinori Sueyoshi,
    ``Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core,''
    IEICE Transactions on Information and Systems, Vol.E100-D，No.4，pp. 633-644, Apr. 2017

    M.Amagasaki, F.Murase, M.Kuga, M.Iida, and T.Sueyoshi,
    ``FPGA based ASIC Emulator with High Speed Optical Serial Link,''
    HEART2017 Proc. of the 8th International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies, Article No. 18, Bochum, Germany, June 2017. doi:10.1145/3120895.3120913

    M.Kuga, K.Fukuda, M.Amagasaki, M.Iida, and T.Sueyoshi,
    ``High-level Synthesis based on Parallel Design Patterns using a Functional Language,''
    HEART2017 Proc. of the 8th International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies, Bochum, Germany, June 2017. doi:10.1145/3120895.3120918

    Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi,
    ``Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost,''
    IPSJ Transactions on System LSI Design Methodology, Vol.10, pp.63-70, Aug. 2017.

    Gololo Doctor, Hendarmawan, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi,
    ``Low-Cost Hardware that Accelerates Frequent Item Counting with an FPGA,''
    IEIE Transactions on Smart Processing and Computing, Vol.6, No.5, pp.347-354, Oct. 2017.

    Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi,
    ``Enabling FPGA-as-a-Service in the Clound with hCODE Platform",
    IEICE Transactions on Information and Systems, Vol.E101-D，No.2，pp. 335-343, Feb. 2018,

    Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida and Toshinori Sueyoshi,
    ``Three dimensional FPGA architecture with fewer TSVs",
    IEICE Transactions on Information and Systems, Vol.E101-D，No.2，pp. 278-287, Feb. 2018

  • 国際会議

    Qian Zhao, Masahiro Iida and Toshinori Sueyoshi,
    ``A Study of FPGA Virtualization and Accelerator Scheduling,''
    The first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters(ETCD2017), April 2017, Xi'an, China (2017/4/8発表)

    M.Amagasaki, F.Murase, M.Kuga, M.Iida, and T.Sueyoshi,
    ``FPGA based ASIC Emulator with High Speed Optical Serial Link,''
    Proc. of International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017), June 2017, Bochum, Germany (2017/6/9発表)

    Purnama, F., Hendarmawan, Andra, M., Usagawa and T. and Iida, M.,
    ``Hand Carry Data Collecting Through Questionnaire and Quiz Alike Using Mini-computer Raspberry Pi,''
    Proc. The International Mobile Learning Festival (IMLF2017), pp.18-32, June 8-10, 2017, Hong Kong.

    Mpho Gift Doctor Gololo, Hendarmawan, Qian Zhao and Masahiro Iida,
    ``Accelerating Frequent Item Count with FPGA,''
    Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2017), OS-12-04, July 2017, Busan, Korea (2017/7/4発表)

    Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi,
    ``High-Performance Data Filtering Processor Design for Database Acceleration using HLS''
    Proc. of 2017 Joint Conference of Electrical, Electronics and Information Engineers in Kyusyu, 09-1P-01, Sep. 2017, Okinawa, Japan (2016/9/27発表)

    Keishiro Akashi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi,
    ``Evaluation 3D-FPGA using TSV physical information,''
    Proc. of 2017 Joint Conference of Electrical, Electronics and Information Engineers in Kyusyu, 09-1P-02, Sep. 2017, Okinawa, Japan (2016/9/27発表)

    Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, and Toshinori Sueyoshi,
    ``hCODE 2.0: An Open-source Toolkit for Building Efficient FPGA-enabled Clouds,’’
    Proc. of International Conference on Field-Programmable Technology(ICFPT17), pp.267-270, Dec. 2017, Melbourne, Australia. (2017/12/12発表)

    Hendarmawan, Fajar Purnama, Tsuyoshi Usagawa and Masahiro Iida,
    ``A study of distributed intranet architecture for educational platform as a solution for Sustainable Development Goals (SDGs),’’
    on The 12th International Student Conference on Advanced Science and Technology (ICAST 2017), Nov. 2017, Kaohsiung, Taiwan. (2017/11発表)(Best Presentation Award)

  • 一般講演発表

    宇都宮誉博，尼崎太樹，飯田全広，久我守弘，末吉敏則
    ``重みの2のべき乗近似を用いたCNNのFPGA実装に関する一検討，''
    信学技報 RECONF2017-6，vol.117，no.46，pp25-30，May 2017. (2017/5/22発表)

    三浦巴慎，尼崎太樹，飯田全広，久我守弘，末吉敏則
    ``任意精度演算可能なビットシリアル演算器の提案，''
    信学技報 RECONF2017-6，vol.117，no.45，pp37-41，May 2017. (2017/5/22発表)

    寺岡拓也，久我守弘，尼崎太樹，飯田全広，末吉敏則
    ``関数型言語における高階関数を利用した高位合成の一検討，''
    信学技報 RECONF2017-35，vol.117，no.221，pp75-80，Sep. 2017. (2017/9/18発表)

    中川裕貴，趙　謙，尼崎太樹，飯田全広，久我守弘，末吉敏則，'
    ``hCODE 2.0: FPGAクラスタシステム向けオープンソース開発管理プラットフォーム"，'
    信学技報 VLD2017-27，vol.117，no.273，pp.1-6，Nov 2017. (2017/11/6発表)
    '
    松崎貴之，尼崎太樹，飯田全広，久我守弘，末吉敏則，'
    ``FPGAを用いたグラフストリーム処理の一検討"，'
    信学技報 RECONF2017-38，vol.117，no.279，pp.7-12，Nov 2017. (2017/11/6発表)

    明石啓司郎，尼崎太樹，飯田全広，久我守弘，末吉敏則，'
    ``Face-down積層型3次元FPGAの性能評価"，'
    信学技報 RECONF2017-42，vol.117，no.279，pp.31-36，Nov 2017(2017/11/7発表)

    宇都宮誉博，尼崎太樹，飯田全広，久我守弘，末吉敏則，'
    ``2のべき乗近似とプルーニングを用いたCNN向けFPGAアクセラレータ "，'
    信学技報 RECONF2017-70，vol.117，no.379，pp.119-124，Jan. 2018.(2018/1/19発表)

    高木大智，趙謙，久我守弘，尼崎太樹，飯田全広，末吉敏則
    ``FPGAの高速シリアル通信を用いたクラスタコンピューティング環境の一検討，''
    火の国情報シンポジウム2018，A6-1，情報処理学会九州支部，pp1-6，March. 2018. (2018/3/2発表)

  • ポスター

    M.Kuga, K.Fukuda, M.Amagasaki, M.Iida, and T.Sueyoshi,
    ``High-level Synthesis based on Parallel Design Patterns using a Functional Language,''
    Proc. of International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2017), June 2017, Bochum, Germany (2017/6/7発表)