My research field is architecture, CAD algorithm for reconfigurable system. If you are interested in my researches and want to know more detail, please contact me.

♢ Three dimensional FPGA Architecture and CAD tools

keywords: 3D-FPGA, face-down stacking, face-up stacking

To balance between cost and performance, and to explore 3D field-programmable gate array (FPGA) with realistic 3D integration processes, we propose spatially distributed and functionally distributed types of 3D FPGA architectures. The functionally distributed architecture consists of two wafers, a logic layer and a routing layer, and is stacked by a face-down process technology. Since vertical wires pass through microbumps, no TSVs are needed. In contrast, the spatially distributed architecture is divided into multiple layers with the same structure, unlike in the functionally distributed type. This architecture can be expanded to more than two layers by stacking multiples of the same die. The goal of this study is to elucidate the advantages and disadvantages of these two types of 3D FPGAs.

♢ Soft error tolerant FPGA Architecture

keywords: Soft error, DMR

Due to reaching the nanoscale transistor size, effect of single event upset (SEU) to the memory has become conspicuous. In small device geometries, a single particle strike might affect multiple adjacent cells in a memory array resulting in a multiple bit upset (MBU). Traditional fault tolerance technologies such as triple modular redundancy (TMR) and error correcting code (ECC) occupy the large area and have vulnerability to MBU. In this research, we propose DMR based error correct circuit and employ a combination of proposed circuit and the interleaving technique to mitigate MBU. In addition, we explain soft error simulator developed to calculate bit interleaving distance.

♢ Hard error tolerant FPGA Architecture

keywords: Hard error, Error detection and correction

In this research, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in (A-6) system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for singlecycle reconfiguration. In addition, we utilize routing tools, namely Easy-Router for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores.

♢ FPGA placement based on SOM

keywords: SOM, Topology free FPGA placement

A wide variety of field-programmable gate array (FPGA) routing structures have been proposed, as exemplified by three-dimensional stack and hierarchical-type FPGAs. However, since traditional FPGA tools are limited to island-style routing architectures, great effort is needed to construct various routing structures. To overcome this problem, we develop an FPGA design framework that is focused on improving on exploration efficiency for various FPGA routing architectures. In this study, we propose an FPGA placement method based on Kohonen self-organizing maps (SOMs). SOMs are one type of unsupervised learning artificial neural network. Because a lattice structure is typically used for the output layer of an SOM, the routing structure (routing topology) of an FPGA can be directly represented by the output layer. This is known as topological mapping, and it allows for various FPGA routing structures to be handled flexibly. We report the result of experimentally evaluating two types of FPGA structures: hierarchical fault-tolerant FPGAs and three dimensional FPGAs.

♢ Acceleration of machine learning with low area/power

keywords: Machine learning, Deep learning, Neural Network

Machine learning and deep learning are one of hottest topic in AI field. It's intended to bring super intelligent models extracted from deep learning at data centers – over to mobile and wearable devices. We are trying to implement these algorithms on FPGA effectively. This research just started this year.