Profile

Present : Postdoctoral Researcher at Faculty of Advanced Science and Technology of Kumamoto University, Japan.
2014 : Received the Doctor of Engineering degree from Computer Science and Electrical Engineering College of Kumamoto University, Japan.
2011 : Received the M.E. degree from Computer Science and Electrical Engineering College of Kumamoto University, Japan.
2007 : Received the B.E. degree from the Control Engineering and Science College of Qingdao University of Science and Technology, China.

Publications

Articles

  1. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, "Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost", IPSJ Transactions on System LSI Design Methodology, Vol.10, pp.63-70, Aug. 2017.  [PDF]

  2. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, "A 3D FPGA Architecture to Realize Simple Die Stacking", IPSJ Transactions on System LSI Design Methodology, Vol.8, pp.116-122, Aug. 2015.

  3. Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, and Toshinori Sueyoshi, "Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC", IEICE Transactions on Information and Systems, Vol.E98-D, No.2, pp.252-261, Feb. 2015. [IEICE][Sci]

  4. Qian Zhao, Kazuki Inoue, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, and Toshinori Sueyoshi, "FPGA Design Framework Combined with Commercial VLSI CAD", IEICE Transactions on Information and Systems, Vol.E96-D, No.8, pp.1602-1612, Aug. 2013. [IEICE][Sci]

  5. Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, and Toshinori Sueyoshi, "COGRE: A Novel Compact Logic Cell Architecture for Area Minimization", IEICE Transactions on Information and Systems, Vol.E95-D, No.2, pp.294-302 , Feb. 2012. [IEICE][Sci]

  6. Qian Zhao, Y. Ichinomiya, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, "A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems", IEEE Embedded Systems Letters, Vol.3, Issue3, pp.89-92, Sep. 2011. [IEEE]

  7. Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, ``A Variable Grain Logic Cell and Routing Architecture for Reconfigurable IP Core,'' ACM Transactions on Reconfigurable Technology and Systems (TRETS), 4.1, Article 5, 24 pages, DOI 10.1145/1857927.1857932. Dec. 2010. [ACM][Sci]

Conference Papers

  1. Qian Zhao, Masahiro Iida and Toshinori Sueyoshi, "A Study of FPGA Virtualization and Accelerator Scheduling," The first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters(ETCD2017), April 2017.

  2. Qian Zhao,Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, "hCODE: An Open-source Platform for FPGA Accelerators," Proc. of International Conference on Field-Programmable Technology(ICFPT2016), pp.201-204, Dec. 2016.

  3. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, "A Study of Heterogeneous Computing Design Method based on Virtualization Technology," Proc. of the 2016 International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016), pp.105-110, July. 2016.

  4. M.Amagasaki, Yuto Takeuchi, Qian Zhao, M.Iida, M.Kuga and T.Sueyoshi, "Architecture Exploration of 3D FPGA to minimize internal layer connection," Proc. 23rd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC2015), pp.110-115, Oct. 2015. [IEEE]

  5. M.Amagasaki, Qian Zhao, M.Iida, M.Kuga and T.Sueyoshi, "A CONFIGURATION MEMORY REDUCED PROGRAMMABLE LOGIC CELL," Proc. of IEEE Symposium on COOL Chips XVIII, Session IV-6, Apr. 2015.

  6. M.Amagasaki, Qian Zhao, M.Iida, M.Kuga and T.Sueyoshi, ``Simple Wafer Stacking 3D-FPGA Architecture,'' Proc. of the 2015 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), K-3, June 2015.

  7. T.Kajiwara, Qian Zhao, M.Amagasaki, M.Iida, M.Kuga and T.Sueyoshi, ``A Novel Three-dimensional FPGA Architecture with High-speed Serial Communication Links,'' Proc. International Conference on Field Programmable Technology(ICFPT2014), pp.306-309, Dec. 2014.

  8. Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, ``A Logic Cell Architecture Exploiting the Shannon Expansion for the Reduction of Configuration Memory,'' Proc. 24th International Conference on Field Programmable Logic and Applications(FPL2014), Sep. 2014. [IEEE]

  9. J.Zhang, Qian Zhao, M.Kuga, M.Amagasaki, M.Iida and T.Sueyoshi, ``A Comparison of Sorting Algorithms with FPGA Acceleration by High Level Synthesis,'' Proc. 2014 Joint Conference of Electrical and Electronics Engineers in Kyusyu, 08-1P-02, pp.200-201, Sep. 2014.

  10. Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, ``Three-Dimensional Stacking FPGA Architecture Using Face-to-Face Integration,'' Proc. 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC2013), pp.196-201, Oct. 2013. [IEEE]

  11. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, ``An FPGA Design and Implementation Framework Combined with Commercial VLSI CADS,'' Proc. International Conference on 8th International Workshop on Reconfigurable Communication-centri Systems-on-Chip(ReCoSoC2013), Jul. 2013. [IEEE]

  12. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, ``An Automatic FPGA Design and Implementation Framework,'' Proc. 23th International Conference on Field Programmable Logic and Applications(FPL2013), Sep. 2013. [IEEE]

  13. Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, ``DEFECT-ROBUST FPGA ARCHITECTURES FOR INTELLECTUAL PROPERTY CORES IN SYSTEM LSI,'' Proc. 23th International Conference on Field Programmable Logic and Applications(FPL2013), Sep. 2013. [IEEE]

  14. Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, ``An Automatic Design and Implementation Framework for Reconfigurable Logic IP Core,'' Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA2013), pp.36-42, Jul. 2013.

  15. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, ``A Novel FPGA Design Framework with VLSI Post-routing Performance Analysis,'' Proc. International 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays(FPGA2013), pp.271, Feb. 2013. [ACM]

  16. Qian Zhao, Y. Iwai, M. Amagasaki, M. Iida and T. Sueyoshi ``A Novel Reconfigurable Logic Device Base on 3D Stack Technology,'' Proc. International 3D System Integration Conference(3DIC2011), P-2-14, pp.1-4, Osaka, Japan, Feb. 2012. [IEEE]

  17. Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, ``A Robust Reconfigurable Logic Device Based on Less Configuration Memory Logic Cell (FPT2010),’’ Proc. of International Conference on Field-Programmable Technology(ICFPT10), pp.162-169, Beijing, China, Dec. 8-10, 2010. [IEEE]

  18. Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, ``A Less Configuration Memory Reconfigurable Logic Device with Error Detect and Correct Circuit,'' Proc. of IEEE Region 10 International Technical Conference (TENCON2010), T6-2.3, Fukuoka, Japan, Nov. 21-24, 2010. [IEEE]

  19. Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Hiroki Yosho, Komei Yoshizawa, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, and Toshinori Sueyoshi, ``A Prototype Chip of Reconfigurable Logic Device using Variable Grain Logic Cell Architecture", Proc. of IEEE Region 10 International Technical Conference (TENCON2010), T6-2.3, Fukuoka, Japan, Nov. 21-24, 2010. [IEEE]

  20. K.Yoshizawa, K.Inoue, Y.Okamoto, Qian Zhao, H.Yosho, M.Koga, M.Amagasaki, M.Iida, M.Kuga, and T.Sueyoshi, ``Design of Prototype Chip Based on Variable Grain Logic Cell Architecture", Proc. the 4th International Student Conference on Advanced Science and Technology (ICAST2010), pp213-214, Izmir, Turk, May 2010.

  21. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, ``A Study of Local Interconnect Architecture for Variable Grain Logic Cell", The 2nd International Student Conference on Advanced Science and Technology (ICAST), pp.93-94, Beijing, China, December 22-23, 2008.

  22. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi, ``Efficient Permutation-based Boolean Matching for VGLC Technology Mapping,'' Proc. 2008 Joint Conference of Electrical and Electronics Engineers in Kyusyu, 12-1P-05, Oita, Japan, Sep. 2008.

General Lectures

  1. 趙 謙, `` hCODE:FPGAアクセラレータのためのオープンソースプラットフォーム,'' CEATEC2016半導体/プログラマブルデバイスプラザ,Oct. 2016.

  2. 池邊雅登,趙 謙, 尼崎太樹,飯田全広,久我守弘,末吉敏則 ``3次元FPGA向け消費電力解析ツール,'' 信学技報 RECONF2016-46,vol.116,no.332,pp35-40,Nov. 2016.

  3. 中道拓也,趙 謙,尼崎太樹,飯田全広,久我守弘,末吉敏則 ``hCODE:FPGAアクセラレータのためのオープンソースプラットフォーム,'' 信学技報 RECONF2016-34,vol.116,no.210,pp45-50,Sep. 2016.

  4. 竹内悠登,趙 謙, 尼崎太樹,飯田全広,久我守弘,末吉敏則 `` 高速シリアル通信機構をもつ3次元FPGAの面積最適化,'' 信学技報 RECONF2015-4,vol.115,no.109,pp17-22,Jun. 2015.

  5. 趙 謙,尼崎太樹,飯田全広,久我守弘,末吉敏則, ``レイヤ間接続を削減した3次元FPGAアーキテクチャの検討,'' 信学技報 RECONF2014-53,vol.114,no.428,pp.41-46,Jan. 2015.

  6. 尼崎太樹, 井上万輝, 趙 謙, 飯田全広, 久我守弘, 末吉敏則, ``故障耐性をもつFPGA-IPコアの提案,'' 信学技報 RECONF2013-13,pp.62-72,May 2013.

  7. 岩井佑介,趙 謙, 尼崎太樹,飯田全広,久我守弘,末吉敏則, ``配線領域を分割した三次元FPGAの一提案,'' 信学技報 RECONF2012-63,vol.112,no.377,pp.13-18,Jan. 2013.

  8. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi, ``A Design Framework for reconfigurable IPs with VLSI CADs,'' 信学技報 RECONF2012-41,vol.112,no.203,pp.101-106,Sep. 2012.

  9. 岩井佑介,趙 謙, 尼崎太樹,飯田全広,久我守弘,末吉敏則, ``三次元積層技術を用いたFPGA配線構造の一提案,'' 若手の会セミナー2012講演論文集,情報処理学会九州支部,pp.29-33,Sep. 2012.

  10. 岩井佑介,趙 謙, 尼崎太樹,飯田全広,久我守弘,末吉敏則, ``コネクションブロックの3次元接続を用いたFPGAチップ面積の削減,'' LSIとシステムのワークショップ2012予稿集,pp.231-233,May. 2012.

  11. Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida and Toshinori Sueyoshi, ``An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device,'' 信学技報 RECONF2010-32,vol.110,no.204,pp.85-90,Sep. 2010.

  12. 井上万輝,岡本康裕,趙 謙,吉澤孔明,用正博紀,古賀正紘,尼崎太樹,飯田全広,久我守弘,末吉敏則, ``粒度可変論理セルをもつ再構成論理デバイスの設計と試作,'' 信学技報, vol. 109, no. 395, RECONF2009-64, pp. 59-64,Jan. 2010.

  13. Qian Zhao,Masahiro Koga,Motoki Amagasaki,Masahiro Iida,Toshinori Sueyoshi, ``A Boolean Matching Method for VGLC Technology Mapping,'' 情報処理学会九州支部若手の会,pp.23-24,Sep. 2008.

Awards

  1. 2015, 優秀リコンフィギャラブルシステム論文賞(Transactions[5]).

  2. 2012, 4th Place of HEART2012 Connect6 Competition.

  3. 2009, 情報処理学会九州支部奨励賞.

  4. 2008, 情報処理学会九州支部若手の会セミナー賞.


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