`include "alu_op.v" module dec_seq ( ... ); ...... reg ICS, HALT; ...... reg [3:0] ALU; //------------------------------------------------------------------// // Controls //------------------------------------------------------------------// always @( STATE or FR or IR ) begin ICS <= 0; HALT <= 0; DBI1 <= 0; DBI2 <= 0; MREQ <= 0; IORQ <= 0; RW <= 0; ACC_R <= 0; ACC_W<= 0; IXR_R <= 0; IXR_W<= 0; SP_R <= 0; SP_W <= 0; PC_R <= 0; PC_W <= 0; PC_I <= 0; AR_W1 <= 0; AR_W2<= 0; IR_R12<= 0; IR_R8P1<= 0; IR_R8P2<=0; IR_R8M2<=0; IR_W<=0; FR_W <= 0; ALU <= `IPAS; case ( STATE ) `HALTING : HALT<=1; `V1 : MREQ<=1; `V2 : begin MREQ<=1; PC_W<=1; DBI1<=1; end `F1 : begin PC_R<=1; AR_W2<=1; PC_I<=1; end `F2 : MREQ<=1; `F3 : begin MREQ<=1; IR_W<=1; DBI1<=1; end // `DEC : // // LD Imm. // `LDI_1 : begin IR_R8P1<=1; ACC_W<=1; ICS<=1; end // // LD index // `LDX_1 : begin IXR_R<=1; AR_W1<=1; IR_R8P2 <= !SIGN; IR_R8M2 <= SIGN; ALU <= `IADD; end `LDX_2 : MREQ<=1; `LDX_3 : begin MREQ<=1; ACC_W<=1; DBI1<=1; ICS<=1; end // // LD Direct // `LDD_1 : begin IR_R12<=1; AR_W2<=1; end `LDD_2 : MREQ<=1; `LDD_3 : begin MREQ<=1; DBI1<=1; ACC_W<=1; ICS<=1; end // // ST index // `STX_1 : begin ...... ; ...... ; ...... ; ...... ; ...... ; end `STX_2 : begin ...... ; ...... ; end `STX_3 : begin ...... ; ...... ; ...... ; end `STX_4 : begin ...... ; ...... ; ...... ; end // // ST Direct // `STD_1 : begin ...... ; ...... ; end `STD_2 : begin ...... ; ...... ; end `STD_3 : begin ...... ; ...... ; ...... ; end `STD_4 : begin ...... ; ...... ; ...... ; end // // CALL // `CALL_1: begin ...... ; ...... ; ...... ; ...... ; end `CALL_2: begin ...... ; ...... ; end `CALL_3: begin ...... ; ...... ; ...... ; end `CALL_4: begin ...... ; ...... ; end `CALL_5: begin ...... ; ...... ; ...... ; end // // Branch Instructions // `JP_1 : begin ...... ; ...... ; ...... ; end // // Binary Instructions // ADD, SUB, OR, EOR, AND `BIOP_IMM_1 : begin ...... ; ...... ; ...... ; ...... ; ...... ; ...... ; ...... ; end // // BIOP Index // ADD, SUB, OR, EOR, AND `BIOP_IDX_1 : begin IXR_R<=1; AR_W1<=1; IR_R8P2 <= !SIGN; IR_R8M2 <= SIGN; ALU <= `IADD; end `BIOP_IDX_2 : MREQ<=1; `BIOP_IDX_3 : begin MREQ<=1; ACC_R<=1; ACC_W<=1; ALU<=`OP_A; FR_W<=1; DBI2<=1; ICS<=1; end // // INC & DEC & MV // `INC_DEC_MV : begin case ( `OP_S ) `RD_ACC : ...... ; `RD_SP : ...... ; `RD_IXR : ...... ; `RD_PC : ...... ; endcase case ( `OP_D ) `RD_ACC : ...... ; `RD_SP : ...... ; `RD_IXR : ...... ; `RD_PC : ...... ; endcase case ( `OP_6 ) `IR_INC : begin ...... ; ...... ; end `IR_DEC : begin ...... ; ...... ; end endcase ...... ; end // Mono operand instructions // NOT and all shift instructions `MONO_1 : begin ...... ; ...... ; ...... ; ...... ; ...... ; end // // INPUT instruction // `IN_1 : begin ...... ; ...... ; end `IN_2 : ...... ; `IN_3 : begin ...... ; ...... ; ...... ; ...... ; end // // OUTPUT instruction // `OUT_1 : begin ...... ; ...... ; end `OUT_2 : begin ...... ; ...... ; end `OUT_3 : begin ...... ; ...... ; ...... ; end `OUT_4 : begin ...... ; ...... ; ...... ; end // // POP // `POP_1 : begin ...... ; ...... ; ...... ; ...... ; end `POP_2 : ...... ; `POP_3 : begin ...... ; ...... ; ...... ; ...... ; end // // PUSH // `PUSH_1 : begin ...... ; ...... ; ...... ; ...... ; end `PUSH_2 : begin ...... ; ...... ; end `PUSH_3 : begin ...... ; ...... ; ...... ; end `PUSH_4 : begin ...... ; ...... ; ...... ; end // // RET // `RET_1 : begin ...... ; ...... ; ...... ; ...... ; end `RET_2 : ...... ; `RET_3 : begin ...... ; ...... ; ...... ; ...... ; end // // HALT // `HALT_1 : begin HALT<=1; ICS<=1; end // // NOP // `NOP_1 : ICS<=1; endcase end