//
// Test Module for KITE-1 Micorprocessor
//
`timescale 1ns/1ns
module kite_test;

  initial
  begin
     $shm_open("waves.shm");
     $shm_probe("as");
  end

wire  ACC_R, ACC_W, AR_W, FR_W, HALT, IORQ, IR_R, IR_W, IXR_R, IXR_W, 
      MREQ, PC_I, PC_R, PC_W, RW, SP_R, SP_W,
      S, Z, V, C, ICS;

reg  ACK, CLOCK, RESET, MUX;

wire [15:0]  ADDR;
wire [11:0]  SP;
wire [11:0]  IXR;
wire [11:0]  PC;
wire [15:0]  ACC, IR;

wire [15:0]  DATA;

reg  [15:0] io_DATA;


// Inout assignments 
data_alias data_alias (DATA, io_DATA);


kite_top kite_top(DATA, ADDR, MREQ,  IORQ,  RW, ACK,
                  CLOCK, RESET, ICS, ICSO,  HALT,
                  ACC, ACC_R, ACC_W, 
                  IXR, IXR_R, IXR_W,
                  IR,  IR_R,  IR_W, 
                  PC, PC_I, PC_R, PC_W,
                  AR_W,
                  SP, SP_R, SP_W,
                  S, Z, V, C,  FR_W, DBI, DBO, MUX );
 
//
// CLOCK : 1MHz infinite loop
//
initial
begin
    CLOCK = 1'b1;
    while(1)
        CLOCK = #500 ~CLOCK;
end

//
// MUX : 2MHz infinite loop
//
initial
begin
    MUX = 1'b1;
    while(1)
        MUX = #250 ~MUX;
end

//
// Condition for Termination : IR = HALT and HALT = TRUE
//
always @( IR or HALT )
  if( IR == 16'hF800 && HALT == 1'b0 )
    #10000 $finish;

//
//  RESET
//

initial
begin
    RESET = #    0 1;	//     0ns 
    RESET = #  300 0;	//   300ns
    RESET = # 3200 1;	//  3500ns
end

//
// Load instructions on Memory
//

reg [15:0] MEM[0:4095];	// Memory Image
integer n;		// for Memory Initialize

initial
begin
  for (n = 0; n < 16'hffff; n = n + 1)
    MEM[n] = 16'h0000;
  $readmemh("testadd.ram", MEM);	// Memory Image File
end

//
// Memory and I/O Transactions
//
initial
begin
    ACK  = # 0 1;	//     0ns 
end

reg [15:0] OUTR;	// OUT port

initial
begin
    OUTR  = # 0 16'h0000;	//     0ns 
end

always @( MREQ )
begin
  if ( MREQ == 1'b0 && RW == 1'b1 )
    begin
      io_DATA = MEM[ADDR];
      ACK     = 1'b0;
//      $display("MEM Transaction READ  : ADDR=%x  DATA=%x", ADDR, MEM[ADDR]);
    end
  else if ( MREQ == 1'b1 && RW == 1'b1 )
    begin
      io_DATA = 16'hZZZZ;
      ACK     = 1'b1;
    end
  else if ( MREQ == 1'b0 && RW == 1'b0 )
    begin
      MEM[ADDR] = DATA[15:0];
      ACK     = 1'b0;
//      $display("MEM Transaction WRITE : ADDR=%x  DATA=%x", ADDR, DATA);
    end
  else if ( MREQ == 1'b1 && RW == 1'b0 )
    begin
      ACK     = 1'b1;
    end
end

always @( IORQ )
begin
  if ( IORQ == 1'b0 && RW == 1'b1 )
    begin
      if ( ADDR == 16'h0000 )
        begin
          io_DATA = 16'h000a;				// Input Value
          ACK     = 1'b0;
        end
      else
        begin
          io_DATA = 16'hZZZZ;
          ACK     = 1'b1;
      end
//      $display("I/O Transaction INPUT : ADDR=%x  DATA=%x", ADDR, io_DATA);
    end
  else if ( IORQ == 1'b1 && RW == 1'b1 )
    begin
      io_DATA = 16'hZZZZ;
      ACK     = 1'b1;
    end
  else if ( IORQ == 1'b0 && RW == 1'b0 )
    begin
      ACK     = 1'b0;
      OUTR    = DATA;
//      $display("I/O Transaction OUT   : ADDR=%x  DATA=%x", ADDR, DATA);
    end
  else if ( IORQ == 1'b1 && RW == 1'b0 )
    begin
      ACK     = 1'b1;
    end
end

//
// Execution Trace
//
always @( posedge ICS )
begin
//if( $time > 5000 )
     #500 $display("  %s%s%s%s acc=%x ixr=%x sp=%x out=%x pc=%x     %x",
	( S == 1'b0 ) ? "M" : "-",
	( V == 1'b0 ) ? "V" : "-",
	( Z == 1'b0 ) ? "Z" : "-",
	( C == 1'b0 ) ? "C" : "-",
	ACC, IXR, SP, OUTR, PC, MEM[PC]);
end

endmodule


module data_alias( alias_sig_o, alias_sig_i);

input  [15:0] alias_sig_i;
output [15:0] alias_sig_o;

assign alias_sig_o = alias_sig_i;

endmodule