`define HMAX 100 // H total Char.
`define HSIZ 80 // H Size
`define HSP 84 // H Sync. Pos.
`define HSL 12 // H Sync. Len.
`define HCR 8 // H dots per Char.
`define VMAX 26 // V total Char.
`define VSIZ 24 // V Size
`define VSP 25 // V Sync. Pos.
`define VSL 1 // V Sync. Len.
`define VCR 20 // V lines per Char.
module vram ( CLK, DCLK, RST, ADDR, DATAI, DATAO, MREQ, RW, ACK, R, G, B, HS, VS, DE );
input ...;
output ...;
...
endmodule
$B$^$?!"%+%&%s%?$N@k8@$O0J2<$N$H$*$j$H$J$k!#(B
reg [2:0] CNT;
reg [6:0] HCNT; // H Counter 0-99
reg [4:0] VCNT; // V Counter 0-27
reg [4:0] RCNT; // R Counter 0-19
VideoRAM$B$H(BChar.ROM$B$N%"%/%;%9J}K!(B
VGA$B%b%K%?$X$N2hA|I=<($O!"DL>o$N%F%l%S$HF1MM$K%i%9%?%9%-%c%s$GI=<($r9T$C(B
$B$F$$$k!#(B
- $B%/%m%C%/$O(B75MHz$B$H(B25MHz$B$,6!5k$5$l$F$$$k!#(B
KITE$B%W%m%;%C%5$+$i$N(BVRAM$B%"%/%;%9$O(B75MHz$B$KF14|$9$k!#(B
VGA$B%3%s%H%m!<%kIt$O$9$Y$F(B1dot$B$N%/%m%C%/$G$"$k(B25MHz$B$r4pK\$H$7$FF0:n$7$F$$$k!#(B
- $B?^$K<($9$h$&$K(B1$BJ8;z$N2#$O(B3.125MHz$B$H$J$k!#(B
25MHz$B$r%7%U%H%/%m%C%/(B(1$B%I%C%HJ,$NI=<(%/%m%C%/(B)$B!"(B
25MHz$B$r(B8$BJ,<~$7$?(B3.125MHz$B$G%G%e!<%F%#Hf(B1/8$B$N%/%m%C%/$r%Q%$%W%i%$%s%l%8%9%?MQ$N%?%$(B
$B%_%s%0%/%m%C%/$H$9$k!#(B
$B=PNO?.9f(B
DVI$B%S%G%*$N(BR, G, B$B$N3F=PNO$O(B8$B%S%C%H$G(B256$B3,D4$G$"$k!#(B
$B$7$+$7!":#2s$N@_7W$OC1?'$G$"$k$N$G!"8w$i$;$k>l9g$O(BR,G,B$B$H$b$K(B(FF)$B!"(B
$B8w$i$;$J$$>l9g$O(B(00)$B$r=PNO$9$k!#(B
HS, VS$B$NF14|?.9f$OIiO@M}$G$"$k$N$GCm0U$9$k!#(B
DE$B$OJ8;z$rI=<($5$;$k4|4V$K#1$H$9$k!#(B
$B$J$*!"%Q%$%W%i%$%sF0:n$7$F$$$k$?$a!"(B
HCNT$B$NCM$,(B0$A!+(B79$B$N$H$-$K(BDE$B$r#1$K$9$k$N$G$O$J$$$3$H$KCm0U$9$k!#(B
$B:G8e$K!"(Bkite_top$B3,AX$+$i$O0J2<$NMM$K8F$S=P$9$3$H$K$J$k!#(B
RST$B$H$7$F(BLOCKED$B?.9f$rMQ$$$F$$$k$N$O!"(BPLL$B$K$h$k%/%m%C%/$,0BDj$7$F$+$i(B
$B%3%s%H%m!<%k2sO)$rF0:n$5$;$k$?$a$G$"$k!#(B
//
// Memory & Video RAM
//
vram mem1 ( .CLK (CLK75),
.DCLK(CLK25),
.RST(!LOCKED),
.ADDR(ADR),
.DATAI(DATAO[7:0]),
.DATAO(VRAM_DATAO),
.MREQ(MREQ),
.RW(RW),
.ACK(VRAM_ACK),
.R(R),
.G(G),
.B(B),
.HS(HS),
.VS(VS),
.DE(DE)
);
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