//
// KITE-1 core module
//

module kite( DATA1,			// 1st DATA Bus
             DATA2,			// 2st DATA Bus
             ADDR,			// Address Bus
             HALT,			// HALT Signal
             MREQ,  IORQ, ACK, RW,	// Memory Interface
             CLK,   RST,  ICS,		// System Interface
             DBI1,  DBI2, 
             O_ACC, O_IR, O_IXR, O_SP,	// Observation for Registers
             O_PC,  O_FR,
             ACC_R, ACC_W,		// Read/Write for ACC
             IXR_R, IXR_W,		// Read/Write for IXR
             SP_R,  SP_W,		// Read/Write for SP
             PC_R,  PC_W, PC_I,		// Read/Write/Inc. for PC
             AR_W,  			//      Write for AR
             IR_R, IR_W,		// Read/Write for IR
             FR_W );			//      Write for FR

  inout  [15:0] DATA1;			// 1st DATA Bus
  input  [15:0] DATA2;			// 2nd DATA Bus
  output [11:0] ADDR;			// Address Bus
  output        HALT;
  output        MREQ,  IORQ,  RW;
  output        DBI1,  DBI2;
  input         RST, CLK, ACK;
  output        ICS;

  output [15:0] O_ACC, O_IR;		// ACC and IR
  output [11:0] O_IXR, O_SP, O_PC; 	// IXR and SP and PC
  output [ 3:0] O_FR;			// FR
  output        ACC_R, ACC_W,		// Register Controls
                IXR_R, IXR_W,
                SP_R,  SP_W,
                PC_R,  PC_W,  PC_I,
                AR_W,  IR_R,  IR_W,
                FR_W;

//
// Internal Wires
//
  wire   [15:0] DATA3;		// for DATA Bus 3
  wire   [ 3:0] ALU_C;		// for ALU Control
  wire   [ 3:0] FLAG,  FLAGR;	// for FLAG in/out
  wire   [15:0] IRR;		// for IR out
  wire   IR_R;			// for IR read
  wire   AR_W1, AR_W2;		// for AR write

//
// Module Connections
//

  alu  I_alu (DATA1, DATA2, ALU_C, DATA3, FLAG);
  fr   I_fr  (FLAG,  FLAGR, CLK,   RST,   FR_W);
  assign O_FR = FLAGR;

  acc  I_acc (DATA3,       DATA1,       O_ACC, CLK, RST, ACC_W, ACC_R);
  r12  I_ixr (DATA3[11:0], DATA1,       O_IXR, CLK, RST, IXR_W, IXR_R);
  r12  I_sp  (DATA3[11:0], DATA1,       O_SP,  CLK, RST, SP_W,  SP_R );
  pc   I_pc  (DATA3[11:0], DATA1,       O_PC,  CLK, RST, PC_W,  PC_R, PC_I);
  ar   I_ar  (DATA3[11:0], DATA1[11:0], ADDR,  CLK, RST, AR_W1, AR_W2);
  assign AR_W = AR_W1 | AR_W2;

  ir   I_ir  (DATA1, DATA1, DATA2, IRR, CLK, RST, IR_W,
                                   IR_R12, IR_R8P1, IR_R8P2, IR_R8M2 );
  assign O_IR = IRR;
  assign IR_R = IR_R12 | IR_R8P1 | IR_R8P2 | IR_R8M2 ;

  dec_seq decseq(FLAGR,			// Flag Register
                 IRR,			// Instruction Register
                 CLK,			// Clock
                 RST,			// Reset
                 ACK,			// Memory Acknowledge
                 ICS,			// Instruction Complete Signal
                 HALT,			// HALT state
		 DBI1,    DBI2,		// Input control for Bidir. Buffer
                 MREQ,			// Memory Request
                 IORQ,			// I/O Request
                 RW,			// Read/Write 
		 ACC_R,   ACC_W,	// ACC Control
		 IXR_R,   IXR_W,	// IXR Control
		 SP_R,    SP_W,		// SP  Control
		 PC_R,    PC_W,   PC_I,	// SP  Control
		 AR_W1,   AR_W2,	// AR  Control
		 IR_R12,  IR_R8P1, 	// IR  Control
                 IR_R8P2, IR_R8M2, IR_W,
		 FR_W,			// FR  Control
		 ALU_C );		// ALU Control

endmodule