reg    [2:0] CNT;
reg    [6:0] HCNT;  // H Counter 0-99
reg    [4:0] VCNT;  // V Counter 0-27
reg    [4:0] RCNT;  // R Counter 0-19

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`define HMAX 100 // H total dots
`define HSIZ  80 // H Size
`define HSP   84 // H Sync. Pos.
`define HSL   12 // H Sync. Len.
`define HCR    8 // H dots per Char.
`define VMAX  26 // V total Line
`define VSIZ  24 // V Size
`define VSP   25 // V Sync. Pos.
`define VSL    1 // V Sync. Line
`define VCR   20 // V lines per Char.

module vram (CLK, DCLK, RST, ADDR, DATAI, DATAO, MREQ, RW, ACK, R, G, B, HS, VS, DE);
   input         CLK,	     // Processor Clock (75MHz)
                 DCLK,	     // Video Clock     (25MHz)
                 RST;	     // Reset
   input  [11:0] ADDR;	     // Video Memory Address
   input  [ 7:0] DATAI;	     // Data Input
   input         MREQ,	     // Memory Request
                 RW;	     // Read/Write
   output [ 7:0] DATAO;      // Data Output
   output        ACK;	     // Acknowledge
   output [ 7:0] R, G, B;    // RGB Data
   output        HS, VS, DE; // Sync. & Data Enable

   reg    [ 7:0] DATAO;

   // Memory
   reg    [ 7:0] VRAM [0:2047];
   reg    [ 7:0] CGROM[0:4095];

   // Counter
   reg    [..:0] CNT;	// Character Counter (8dots)
   reg    [..:0] HCNT;  // H Counter 0-99
   reg    [..:0] VCNT;  // V Counter 0-27
   reg    [..:0] RCNT;  // R Counter 0-18

   wire          CEP;	// Character End Pulse

   // Pipeline Register
   reg    [..:0] CADR;	// Character Code (8bits)
   reg    [..:0] SR;	// Shift Register (8bits)

   // Internal Signals
   wire   [..:0] VADR;  // VideoRAM Address (2048bytes)
   wire   [..:0] CGADR; // CG-ROM Address (4096bytes)
   wire   [..:0] CGDATA;// CG-ROM Data Size (8bits)


  // Memory Initialize
  initial
    begin
      $readmemh( "VRAM20.ram", VRAM );
      $readmemh( "font9x18_256.ram", CGROM );
    end

   // Video-RAM Write & Read
   always @( posedge CLK )
   begin
     if( ( ADDR[...] == 1'b1 ) && MREQ && ( RW == ...  ) )
         VRAM[ ...[...:...] ] <= ...;
         ... <= VRAM[ ...[...:...]];
   end

   // Video-RAM Acknowledge for Write & Read 
   assign ACK = ( ( ADDR[...] == 1'b1 ) && ... );

   // Counter for Character End Pulse
   always @( posedge DCLK )
     if( RST ) ... <= ...     else
               ... <= .......;

   assign ...  = ...;  // Character End Pulse


   always @( posedge DCLK )
   begin
      if( ... ) begin ...<=...; ...<=...; ...<=...; end
      if( ... )
      begin
         if( ... == ... )
         begin
            ... <= ...;
            if( ... == ... )
            begin
               ... <= ...;
               if( ... == ... ) ... <= ...;
               else             ... <= ...;
            end
            else
               ... <= ......;
         end
         else
               ... <= ......;
      end
   end

    // Read character data from VRAM
    always @( posedge DCLK )
    begin
      if( ... )
        begin
          ... <= ...;
        end
    end

   // Internal Memory Address
   assign VADR  = { ..., ... } * 12'd... + { ..., ... };
   assign CGADR = { ..., ...[...:...] };
   assign CGDATA= ...[ ... ];

   // Shift Register
   always @( posedge DCLK )
   begin
      if ( ... ) SR <= ...; else
      if ( ... ) SR <= ...; else
                 SR <= { ..., ... };
   end

   // RGB Data & Data Enable
   assign { R, G, B } = ( ...[...]  && ( RCNT < 16 ) ) ? 24'hffffff : 24'h000000;
   assign DE = ( ( 1 < ... && ... < ... + ... ) && ( ... < ... ) );

   //Sync
   assign HS = ~( HCNT >= ... && HCNT < (... + ...) );
   assign VS = ~( VCNT >= ... && VCNT < (... + ...) );

endmodule

  //
  // Memory & Video RAM
  //
  vram   mem1 ( .CLK (CLK75),
                .DCLK(CLK25),
                .RST(!LOCKED),
                .ADDR(ADR),
                .DATAI(DATAO[7:0]),
                .DATAO(VRAM_DATAO),
                .MREQ(MREQ),
                .RW(RW),
                .ACK(VRAM_ACK),
                .R(R),
                .G(G),
                .B(B),
                .HS(HS),
                .VS(VS),
                .DE(DE)
              );