The flag output is a 4-bit bus and there are sign-flag "S", zero flag "Z", overflow flag "V", carry-flag "C" in it. The order of the bit at the bus is free. The change of the flag depends on each direction and is as follows.
Arithmetic operation
Operation | S | Z | V | C |
---|---|---|---|---|
Addition (ADD) | '1' when result is minus. | '1' when result is zero. | '1' when result is incorrect in signed addition. | '1' when carry occurs in unsigned addition. |
Decrement (DEC) | '1' when result is minus. | '1' when result is zero. | '1' when result is incorrect in signed addition. | '1' when carry occurs in unsigned addition. |
Inclement (INC) | '1' when result is minus. | '1' when result is zero. | '1' when result is incorrect in signed subtranction. | '1' when borrow occurs in unsigned subtraction. |
The subtraction (SUB) | '1' when result is minus. | '1' when result is zero. | '1' when result is incorrect in signed addition. | '1' when borrow occurs in unsigned subtraction. |
Logical operation
Operation | S | Z | V | C |
---|---|---|---|---|
Boolean ADD (OR) | Same as most significant bit. | '1' when result is zero. | always 0. | always 0. |
The exclusive OR (The XOR) | Same as most significant bit. | '1' when result is zero. | always 0. | always 0. |
AND (AND) | Same as most significant bit. | '1' when result is zero. | always 0. | always 0. |
The logical NOT (NOT) | Same as most significant bit. | '1' when result is zero. | always 0. | always 0. |
The shift type direction
The calculation kind | S | Z | V | C |
---|---|---|---|---|
The arithmetic right shift (ASR) | Same as most significant bit. | '1' when result is zero. | It is always 0. | Same as least significant bit. |
The arithmetic left shift (ASL) | Same as most significant bit. | '1' when result is zero. | '1' when bit 15 and bit 14 of operand are different value. | Same as most significant bit. |
The logic right shift (LSR) | Same as most significant bit. | '1' when result is zero. | It is always 0. | Same as least significant bit. |
The logic left shift (LSL) | Same as most significant bit. | '1' when result is zero. | It is always 0. | Same as most significant bit. |
The dextroversion (ROR) | Same as most significant bit. | '1' when result is zero. | It is always 0. | Same as least significant bit. |
The anticlockwise-rotation (ROL) | Same as most significant bit. | '1' when result is zero. | It is always 0. | Same as most significant bit. |
The byte swap (SWP) | Same as most significant bit. | '1' when result is zero. | It is always 0. | It is always 0. |
The special operational function
The calculation kind | S | Z | V | C | |
---|---|---|---|---|---|
The path (PAS) | X | X | X | X | Don't care because it isn't stored in FR. |
Each flag can be generated as follows;
reg V ; // for Overflow always @ (A or B or tmp or CB) case (CB) `IADD : V <= ( ( Condition ) && ( Condition ) ) ? 1 : 0; `ISUB : V <= ( ( Condition ) && ( Condition ) ) ? 1 : 0; `IINC : V <= ( ( Condition ) && ( Condition ) ) ? 1 : 0; `IDEC : V <= ( ( Condition ) && ( Condition ) ) ? 1 : 0; `IASL : V <= ( A[15] != tmp[15] ) ? 1 : 0; default : V <= 0; endcase ... assign F[3] = ...... ; // Sign flag assign F[2] = ...... ; // Zero flag assign F[1] = V; // Overflow flag assign F[0] = ...... ; // Carry flag ...
Next, functional simulation simulation of the KITE ALU.