The creating of CUI module

We create the CUI module for the KITE-1 microprocessor.

The specification of the CUI module

Below figures show the screen structure, the character structure and the memory map for the KITE-1 microprocessor.



The block diagram of the CUI module

The CUI module consists of the following block mainly.

The way of thinking of the CUI image display

The image display to the CUI monitor is displaying by the raster-scan like usual TV. To realize these counters and so on, it will should do following definition beforehand. 
`define HMAX 100 // H total Char.
`define HSIZ    80 // H Size
`define HSP     84 // H Sync. Pos.
`define HSL     12 // H Sync. Len.
`define HCR      8 // H dots per Char.
`define VMAX    26 // V total Char.
`define VSIZ    24 // V Size
`define VSP     25 // V Sync. Pos.
`define VSL      1 // V Sync. Len.
`define VCR     20 // V lines per Char.

(CLK, DCLK, RST, ADDR,) module vram (DATAI, DATAO, MREQ, RW, ACK, R, G, the B, HS, VS,
DE) ;
  input      ; output   ;

  
endmodule
Also, the declaration of the counter becomes following "TOORI". 
reg      [2:0] CNT ;
reg      [6:0] HCNT ;    // H Counter 0-99
reg      [4:0] VCNT ;    // V Counter 0-27
reg      [4:0] RCNT ;    // R Counter 0-19


The way of VideoRAM's and Char.ROM's accessing

The image display to the CUI monitor is displaying by the raster-scan like usual TV.





The output-signal

Each output of R, G, the B of the DVI video is 256 pieces of gradation at 8 bits.
However, because the design this time is monochromatic, when making shine, it outputs the case (00) not to make shine R, G, B together (FF).

The sync signal of HS, VS is careful because it is a negative-logic.

DE is asserted (DE=1) when the character display timing.
Note that character display timing is delayed 2-character timing because of pipelining. So it is careful of not making DEd=1 when the value of HCNT is from 0 to 79.

The sample source

`define HMAX   100 // H total dots
`define HSIZ    80 // H Size
`define HSP     84 // H Sync. Pos.
`define HSL     12 // H Sync. Len.
`define HCR      8 // H dots per Char.
`define VMAX    26 // V total Line
`define VSIZ    24 // V Size
`define VSP     25 // V Sync. Pos.
`define VSL      1 // V Sync. Line
`define VCR     20 // V lines per Char.

module vram ( CLK, DCCLK, RST, ADDR, DATAI, DATAO, MREQ, RW, ACK, R, G, B, HS, VS, DE) ;
   input         CLK,          // Processor Clock (75 MHz)
                 DCLK,         // Video Clock       (25 MHz)
                 RST ;         // Reset
   input  [11:0] ADDR ;        // Video Memory Address
   input  [ 7:0] DATAI ;       // Data Input
   input         MREQ,         // Memory Request
                 RW ;          // Read/Write
   output [ 7:0] DATAO ;       // Data Output
   output        ACK ;         // Acknowledge
   output [ 7:0] R, G, B ;     // RGB Data
   output        HS, VS, DE ;  // Sync. The & Data Enable

   reg     [7:0] DATAO ;

   // Memory
   reg      [7:0] VRAM [0:2047] ;
   reg      [7:0] CGROM [0:4095] ;

   // Counter
   reg      [..:0] CNT ;     // Character Counter (8dots)
   reg      [..:0] HCNT ;    // H Counter 0-99
   reg      [..:0] VCNT ;    // V Counter 0-27
   reg      [..:0] RCNT ;    // R Counter 0-18

   wire          CEP ;     // Character End Pulse

   // Pipeline Register
   reg      [..:0] CADR ;    // Character Code (8bits)
   reg      [..:0] SR ;      // Shift Register (8bits)

   // Internal Signals
   wire     [..:0] VADR ;    // VideoRAM Address (2048bytes)
   wire     [..:0] CGADR ; // CG-ROM Address (4096bytes)
   wire     [..:0] CGDATA;// CG-ROM Data Size (8bits)


  // Memory Initialize
  initial
    begin
      $readmemh ("VRAM20.ram", the VRAM) ;
      $readmemh ("font9x18_256.ram", CGROM) ;
    end

   // Video-RAM Write and Read
   always @ (posedge CLK)
   begin
     if ((ADDR [...] == 1'b1) && MREQ && (RW == ...   ))
         VRAM [... [...:...]]<= ...;
         ... <= VRAM[ ...[...:...]];
   end

   // Video-RAM Acknowledge for Write & Read 
   assign ACK = ( ( ADDR[...] == 1'b1 ) && ... );

   // Counter for Character End Pulse
   always @( posedge DCLK )
     if( RST ) ... <= ...     else
               ... <= .......;

   assign ...  = ...;  // Character End Pulse


   always @( posedge DCLK )
   begin
      if( ... ) begin ...<=...; ...<=...; ...<=...; end
      if( ... )
      begin
         if( ... == ... )
         begin
            ... <= ...;
            if( ... == ... )
            begin
               ... <= ...;
               if( ... == ... ) ... <= ...;
               else             ... <= ...;
            end
            else
               ... <= ......;
         end
         else
               ... <= ......;
      end
   end

    // Read character data from VRAM
    always @( posedge DCLK )
    begin
      if( ... )
        begin
          ... <= ...;
        end
    end

   // Internal Memory Address
   assign VADR  = { ..., ... } * 12'd... + { ..., ... };
   assign CGADR = { ..., ...[...:...] };
   assign CGDATA= ...[ ... ];

   // Shift Register
   always @( posedge DCLK )
   begin
      if ( ... ) SR <= ...; else
      if ( ... ) SR <= ...; else
                 SR <= { ..., ... };
   end

   // RGB Data & Data Enable
   assign { R, G, B } = ( ...[...]  && ( RCNT < 16 ) ) ? 24'hffffff : 24'h000000;
   assign DE = ( ( 1 < ... && ... < ... + ... ) && ( ... < ... ) );

   //Sync
   assign HS = ~( HCNT >=   && HCNT (... + ...) ;
   assign VS = ~(VCNT >=... && VCNT < (... + ...)) ;

endmodule


Lastly, it summons as follows from the kite_top hierarchy.
After the clock by PLL is stable about being using LOCKED signal as RST
It is to work a control circuit. 
  //
  // Memory and Video RAM
  //
  vram   mem1 ( .CLK(CLK75),
                .DCLK(CLK25),
                .RST(!LOCKED),
                .ADDR(The ADR),
                .DATAI(DATAO[7:0]),
                .DATAO(VRAM_DATAO),
                .MREQ(MREQ),
                .RW(RW),
                .ACK(VRAM_ACK),
                .R(R),
                .G(G),
                .B(B),
                .HS(HS),
                .VS(VS),
                .DE(DE)
              ) ;
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