VLOGSRC=kite_test.v \
	kite_top.v \
	kite.v \
	alu.v \
	acc.v \
	fr.v \
	ir.v \
	r12.v \
	pc.v \
	ar.v \
	dec_seq.v \
	memory.v \
	vram.v \
	clk_wiz_0_clk_wiz.v \
	clk_wiz_0.v \
	/opt/xilinx/Vivado/2019.2/data/verilog/src/unisims/IBUF.v \
	/opt/xilinx/Vivado/2019.2/data/verilog/src/unisims/BUFG.v \
	/opt/xilinx/Vivado/2019.2/data/verilog/src/glbl.v \
	/opt/xilinx/Vivado/2019.2/data/verilog/src/unisims/MMCME2_ADV.v

VHDLSRC=rgb2dvi/ClockGen.vhd \
	rgb2dvi/DVI_Constants.vhd \
	rgb2dvi/OutputSERDES.vhd \
	rgb2dvi/SyncAsync.vhd \
	rgb2dvi/SyncAsyncReset.vhd \
	rgb2dvi/TMDS_Encoder.vhd \
	rgb2dvi/rgb2dvi.vhd


compile: vhdl_src vlog_src 
	xelab --debug all kite_test glbl -s kite_test

vlog_src: $(VLOGSRC)
	xvlog $(VLOGSRC)

vhdl_src: $(VHDLSRC)
	xvhdl $(VHDLSRC)