//
// Top Module for KITE-1 Microprocessor
//

module kite_top(DATA,	// Data bus
		ADDR,	// Address bus
		MREQ_L,	// Memory request
		IORQ_L,	// I/O request
		RW_L,	// R/W signal
		ACK_L, 	// Memory acknowledge
                CLOCK,	// Clock
		RESET_L,// Reset
		ICS_L,	// Instruction Compleation Cycle for clock generator
		ICSO_L,	// Instruction Compleation Cycle for observation
		HALT_L, // HALT signal
                ACC,			// Accumlator for observation
		ACC_R_L, ACC_W_L, 	// Read/Write controls for ACC
                IXR,			// Index Register for observation
		IXR_R_L, IXR_W_L,	// Read/Write controls for IXR
                IR,			// Instruction Register for observation
		IR_R_L,	IR_W_L,		// Read/Write controls for IR
                PC,			// Program Counter for observation
		PC_R_L,	PC_W_L,	PC_I_L,	// Read/Write/Inc controls for PC
                AR_W_L,			// Write control for AR
                SP,			// Stack Pointer for observation
		SP_R_L, SP_W_L,		// Read/Write controls for SP
                S_L, Z_L, V_L, C_L,	// Flag Register for observation
		FR_W_L,			// Write signal for FR
		DBI_L, DBO_L,	// Output Enables for bidirectional buffer
		MUX );		// Multiplexing signal for AR/IXR

  inout  [15:0] DATA;
  output [15:0] ADDR;
  output        AR_W_L;

  output [15:0] ACC;
  output [15:0] IR;
  output        ACC_R_L,  ACC_W_L;
  output        IR_R_L,   IR_W_L;

  output        MREQ_L,   IORQ_L;
  output        HALT_L;

  output [11:0] IXR;
  output        IXR_R_L,  IXR_W_L;
  output [11:0] SP;
  output        SP_R_L,   SP_W_L;
  output [11:0] PC;
  output        PC_R_L,   PC_W_L,  PC_I_L;
  output        RW_L;

  output        S_L, Z_L, V_L, C_L;
  output        FR_W_L, ICS_L, ICSO_L;
  output        DBI_L, DBO_L;

  input         ACK_L;
  input         CLOCK;
  input         RESET_L;
  input         MUX;

  //
  // Internal line
  //
  wire [11:0] ADR, IXRI;
  wire [15:0] ACC, IR, DATA1, DATA2;
  wire [ 3:0] FR;
  wire ACC_R, ACC_W;
  wire IXR_R, IXR_W;
  wire SP_R,  SP_W;
  wire PC_R,  PC_W,  PC_I;
  wire AR_W;
  wire IR_R,  IR_W;
  wire FR_W,
       HALT,
       MREQ,  IORQ,  RW;
  wire ACK;
  wire RST;   
  wire ICS;
  wire DBI1,  DBI2;


  //
  // Positive Signal
  //
  assign ADDR = { 4'b0000, ADR };
  assign IXR  = ( MUX ) ? ADR : IXRI ;	// multiplexed

  //
  // Negative Signal
  //
  assign AR_W_L   = ~AR_W;

  assign ACC_R_L  = ~ACC_R;
  assign ACC_W_L  = ~ACC_W;
  assign IR_R_L   = ~IR_R;
  assign IR_W_L   = ~IR_W;

  assign MREQ_L   = ~MREQ;
  assign IORQ_L   = ~IORQ;

  assign HALT_L   = ~HALT;

  assign IXR_R_L  = ~IXR_R;
  assign IXR_W_L  = ~IXR_W;
  assign SP_R_L   = ~SP_R;
  assign SP_W_L   = ~SP_W;
  assign PC_R_L   = ~PC_R;
  assign PC_W_L   = ~PC_W;
  assign PC_I_L   = ~PC_I;
  assign RW_L     = ~RW;

  assign S_L    = ~FR[3];
  assign Z_L    = ~FR[2];
  assign V_L    = ~FR[1];
  assign C_L    = ~FR[0];
  assign FR_W_L = ~FR_W;

  assign ICS_L  = ~ICS;		// for ICS
  assign ICSO_L = ~ICS;		// ICS for observe

  assign ACK    = ~ACK_L;
  assign RST    = ~RESET_L;

  //
  // Bidirectional Buffer and controls
  //
  assign DATA1 = ( DBI1 ) ? DATA  : 16'hZZZZ;
  assign DATA2 = ( DBI2 ) ? DATA  : 16'hZZZZ;
  assign DATA  = ( RW   ) ? DATA1 : 16'hZZZZ;

  assign DBO_L = ~RW;
  assign DBI_L = ~ ( DBI1 | DBI2 );

  //
  // Processor Core
  //
  kite kite( DATA1,				// 1st DATA Bus
             DATA2,				// 2nd DATA Bus
             ADR,				// Address Bus
             HALT,				// HALT Signal
             MREQ,  IORQ,  ACK, RW,	   	// Memory Interface
             CLOCK, RST,   ICS, 		// System Interface
             DBI1, DBI2,			// Bidirectional Buffer Control
             ACC, IR, IXRI, SP,                 // Observation for Registers 
             PC, FR,				                             
             ACC_R, ACC_W,			// Read/Write for ACC        
             IXR_R, IXR_W,			// Read/Write for IXR        
             SP_R,  SP_W,			// Read/Write for SP         
             PC_R,  PC_W,  PC_I,		// Read/Write/Inc. for PC    
     	     AR_W,				//      Write for AR         
             IR_R,  IR_W,			// Read/Write for IR         
             FR_W );				//      Write for FR         

endmodule