reg ICS, HALT;
......
reg [3:0] ALU;
//------------------------------------------------------------------//
// Controls
//------------------------------------------------------------------//
always @( STATE or FR or IR or SIGN or BRANCH )
begin
ICS = 0;
HALT = 0;
DBI1 = 0; DBI2 = 0;
MREQ = 0; IORQ = 0; RW = 0;
ACC_R = 0; ACC_W= 0;
IXR_R = 0; IXR_W= 0;
SP_R = 0; SP_W = 0;
PC_R = 0; PC_W = 0; PC_I = 0;
AR_W1 = 0; AR_W2= 0;
IR_R12= 0; IR_R8P1= 0; IR_R8P2=0; IR_R8M2=0; IR_W=0;
FR_W = 0;
ALU = `IPAS;
case ( STATE )
`HALTING : HALT=1;
`V1 : MREQ=1;
`V2 : begin MREQ=1; PC_W=1; DBI1=1; end
`F1 : begin PC_R=1; AR_W2=1; PC_I=1; end
`F2 : MREQ=1;
`F3 : begin MREQ=1; IR_W=1; DBI1=1; end
// `DEC : // without control
......
......
......
//
// BIOP Index
// ADD, SUB, OR, EOR, AND
`BIOP_IDX_1 :
begin
IXR_R=1; AR_W1=1;
IR_R8P2 = ( SIGN == 0 ) ? 1 : 0;
IR_R8M2 = ( SIGN == 1 ) ? 1 : 0;
ALU = `IADD;
end
`BIOP_IDX_2 : MREQ=1;
`BIOP_IDX_3 : begin MREQ=1; ACC_R=1; ACC_W=1; ALU=`OP_A;
FR_W=1; DBI2=1; ICS=1; end
......
......
endcase
end
My mail address is
kuga@cs.kumamoto-u.ac.jp .
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