#! /usr/local/bin/perl

# make_vector (ver.2)

$debug = 0;

#
# Parameter check
#

if( $#ARGV != 0 ) {
  print STDERR "usage: trans vector_file\n" ;
  exit;
}

#
# File open
#

if( !open( INFILE , $ARGV[0] ) ) {
  print STDERR "Can't open file : ", $ARGV[0], "\n";
  exit;
}

#
# Main Loop
#

$input_mode = 0;
$clock_mode = 0;
$vector_mode= 0;

$total_time = 0;

while( <INFILE> ) {
    chop();
    ( $line ) = /\s*(.*)/;
    ( $sep,$keyword ) = $line =~ /^(#)\s*(\w+)/;

    if( $sep eq "#" && $keyword eq "input" ) {
	$input_mode  = 1;
	$clock_mode  = 0;
	$vector_mode = 0;
	$sig_num = 0;
    } elsif( $sep eq "#" && $keyword eq "clock" ) {
	$input_mode  = 0;
	$clock_mode  = 1;
	$vector_mode = 0;
	$clk_num = 0;
    } elsif( $sep eq "#" && $keyword eq "testvector" ) {
	$input_mode  = 0;
	$clock_mode  = 0;
	$vector_mode = 1;
	$vec_num = 0;

	if( $debug ) {
	    printf "Input Siganl Name (%d)\n", $sig_num;
	    for ( $i = 0 ; $i < $sig_num ; $i++ ) {
		print @in_sig[$i], "\n";
	    }
	}

    } elsif( $sep eq "#" ) {
	;;
    } else {
	if( $input_mode == 1 ) {
	    if( $line ne "" ) {
		@in_sig[$sig_num] = $line;	# input signals
		$sig_num++;
	    }
	}
	if( $clock_mode == 1 ) {
	    if( $line ne "" ) {
		( $sig, $tic ) = $line =~ /(\w*)\s*(\d*)/;
		@clk_sig[$clk_num] = $sig;	# clock signals
		@clk_tic[$clk_num] = $tic;
		$clk_num++;
	    }
	}
	if( $vector_mode == 1 ) {
	    if( $line ne "" ) {
		( $s, $r, $c ) = $line =~ /^(\d*)\s*([0-9a-zA-Z'`\s]*)#*(.*)/;
		@step  [$vec_num] = $s;  # step time
		@vector[$vec_num] = $r;  # vector
		@rem   [$vec_num] = $c;  # comments
		$vec_num++;
		$total_time = $total_time + $s;
	    }
	}
    }
}
    
if( $debug ) {
  for ( $i = 0 ; $i < $clk_num ; $i++ ) {
    print @clk_sig[$i], "-", @clk_tic[$i], "\n";
  }

  for ( $i = 0 ; $i < $vec_num ; $i++ ) {
    print @step[$i], "-", @vector[$i], "-", @rem[$i], "\n";
  }
}
    
#
# output vector with Verilog format
#


for ( $i = 0 ; $i < $clk_num ; $i++ ) {
  print "integer i$i;\n";
  print "initial\nbegin\n";
  print "    @clk_sig[$i] = 1'b1;\n";
  print "    for( i$i=0 ; i$i<", $total_time/@clk_tic[$i]*2+2, " ; i$i=i$i+1 )\n";
  print "        @clk_sig[$i] = #", @clk_tic[$i]/2, " ~@clk_sig[$i];\n";
  print "    \$finish;\n";
  print "end\n\n";
}

for ( $i = 0 ; $i < $sig_num ; $i++ ) {
  print "initial\nbegin\n";
  for ( $j = 0 ; $j < $vec_num ; $j++ ) {
    @v = split( /[ \t\n]+/ , @vector[$j] );
    print "    @in_sig[$i] = # @step[$j] @v[$i];";
    if ( @rem[$j] ne "" ) {
      print "\t// @rem[$j] \n";
    } else {
      print "\n";
    }
  }
  print "end\n\n";
}