Design and Implementation for 8-bit ALU
(Skill up for combinational circuit design in Verilog HDL)

Logial operations

Operation	Behavior	Note
Logical and (AND)	A and B	Bitwise logical AND
Logical or (OR)	A or B	Bitwise Logical OR
Logical not (NOT)	not A	Bitwise not, 1's complement

Shift and exchange operations

Operation	Behavior	Note
Arithmetic shift right (ASR)		Arithmetic right shift, Divid operand A by 2
Arithmetic shift left (ASL)		Arithmetic left shift, Multiply operand A by 2
Nibble swap (SWP)	Exchange upper nibble and lower nibble of operand A	for nibble operation

The followings are steps for design and implementation of the ALU.

• Define input and output variables
• Define operation code
• Describe operations
• Describe flags
• Functional simulation
• Implementation process
• Post-layout simulation with real wire delay.
• Validate behavior of ALU on FPGA