Functional Simulation with Verilog-XL

Test bench for ALU

For functional simulation of ALU, we need a test bench file.
Save the following source code to "alu_test.v" file.

Note that all variable names must be matching in module instantiation.

`timescale 1ns/1ps
`include "alu_op.v"

module alu_test;
  reg  [7:0] A;		// Variables for input are "reg" type
  reg  [7:0] B;
  reg  [2:0] CB;
  wire [7:0] Y;		// Variables for output are "wire" type
  wire [3:0] F;

  wire S, Z, V, C;

  initial			// record the signal changes for "simvision" wave viewer in "Verilog-XL" simulator
  begin
     $shm_open("waves.shm");
     $shm_probe("as");
  end

  `include "alu_test.vct"	// include the test vector from ".vct" file.

  alu U1 ( .A(A), .B(B), .CB(CB), .Y(Y), .F(F) ); // instantiation of ALU module 

  assign S = F[3];
  assign Z = F[2];
  assign V = F[1];
  assign C = F[0];

endmodule

Next, Make test vector .

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