$ verilog alu_test.v alu.v

$ verilog alu_test.v alu.v
Tool:   VERILOG-XL      06.20.001-s   Dec 17, 2011  16:15:54

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Compiling source file "alu_test.v"
Compiling included source file "alu_op.v"
Continuing compilation of source file "alu_test.v"
Compiling included source file "alu_test.vct"
Continuing compilation of source file "alu_test.v"
Compiling source file "alu.v"
Compiling included source file "alu_op.v"
Continuing compilation of source file "alu.v"
Highest level modules:
alu_test

0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in
simulation
End of Tool:    VERILOG-XL      06.20.001-s   Dec 17, 2011  16:15:56
$