Make test vector

As a test vector, we make a "alu_test.vh" for test vector file in verilog HDL form. In this exrcise, "make_vector.pl" command generates test vector from "alu_test.txt" file.

Save the following source code as a "alu_test.txt" file. 

# input 
A[7:0]
B[7:0]
CB[2:0]

# testvector
#   A[7:0]  B[7:0]  CB[2:0] 
100 8'h01 8'h01 `IADD		# add
100 8'h01 8'hFF `IADD
100 8'hFF 8'h01 `IADD
100 8'h80 8'h80 `IADD
100 8'h7F 8'h01 `IADD
100 8'h01 8'hFE `IADD
100 8'hFE 8'h01 `IADD
100 8'hFF 8'hFF `IADD
And then, execute following command to make test vector file "alu_test.vh".. 
$ make_vector.pl alu_test.txt > alu_test.vh

Generated "alu_test.vh" file is like this; 
initial
begin
    A[7:0] = # 100 8'h01;	//  add 
    A[7:0] = # 100 8'h01;
    A[7:0] = # 100 8'hFF;
    A[7:0] = # 100 8'h80;
    A[7:0] = # 100 8'h7F;
    A[7:0] = # 100 8'h01;
    A[7:0] = # 100 8'hFE;
    A[7:0] = # 100 8'hFF;
    A[7:0] = # 100 8'hFF;
end

initial
begin
    B[7:0] = # 100 8'h01;	//  add 
    B[7:0] = # 100 8'hFF;
    B[7:0] = # 100 8'h01;
    ...
    <以下省略>
This "alu_test.vh" files is included from test bench file "alu_test.v".

Next, Execute simulation .

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