Trial Results (1 of 3)
Working Time
Group A : has experience to design KITE with Verilog-HDL
Group B : doesn't have experience to design with Verilog-HDL
Unit : Hours
Graphical HDL Entry Tool
Verilog
HDL
Group A
Group B
Tool Operation
Top Level Layer
ALU
Registers
Decoder & Sequencer
Simulation & Debugging
Total
15.3
1.2
2.0
3.0
3.7
8.0
7.0
24.9
0.5
2.5
6.0
5.0
8.0
4.0
26.0
0.5
1.0
4.0
2.0
7.0
5.5
20.0
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