The input/output definition of the decoder sequencer

In the KITE-1 microprocessor of 3 bus-arrangements, the input/output definition example of the decoder sequencer is as follows. 
module dec_seq ( FR,                      // Flag Register
                 IR,                      // Instruction Register
                 CLK,                     // Clock
                 RST,                     // Reset
                 ACK,                     // Memory and I/O Acknowledge
                 ICS                      // Instruction Complete Signal (The signal which shows being the last cycle of the direction)
                 HALT,                    // HALT state
                 DBI1,    DBI2,           // Input control for Input Buffer
                 MREQ,                    // Memory Request
                 IORQ,                    // I/O Request
                 RW,                      // Read/Write (Write Signal)
                 ACC_R,   ACC_W,          // ACC Control
                 IXR_R,   IXR_W,          // IXR Control
                 SP_R,    SP_W,           // SP  Control
                 PC_R,    PC_W,     PC_I, // PC  Control
                 AR_W1,   AR_W2,          // AR  Control
                 IR_R12,  IR_R8P1,        // IR  Control
                 IR_R8P2, IR_R8M2, IR_W
                 FR_W,                    // FR  Control
                 ALU ) ;                  // ALU Control

        input [3:0] FR ;
        input        
        input        

        //
        // Control Signals
        //
        output       ICS,      HALT,     DBI1, DBI2 ;
        output       
        
        output       
        
        output [3:0] ALU ;

//------------------------------------------------------------------//
// State Transition
//------------------------------------------------------------------//
         
         
         
  end
//------------------------------------------------------------------//
// BRANCH flag and SIGN flag are made from IR and FR
//------------------------------------------------------------------//
         
         
         
  end
//------------------------------------------------------------------//
// Controls
//------------------------------------------------------------------//
         
         
         
  end

endmodule
It finds that the control signal of ALU and the register is taken out as the necessary control-register and the flag-register, the output as the entry in this way. Of course, a control signal to the external memory and I/O, too, is needed.

Next, definition of State and Instruction code attempts to have.

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