The description of State machine
State transition is described according to the state-transition diagram and the direction execution phase table.
The execution phase bill refer to the following.
Execution phase table of 3 bus-arrangements
reg [7:0] STATE ; // Current State
//------------------------------------------------------------------//
// State Transition
//------------------------------------------------------------------//
always @ (posedge RST or posedge CLK)
begin
if (RST==1) STATE<=`V0;
else
case ( STATE )
`HALTING : if( RST==1 ) STATE<=`V0;
`V0 : if( RST==0 ) STATE<= ...... ;
`V1 : if( ACK==1 ) STATE<= ...... ;
`V2 : STATE<= ...... ;
`F1 : STATE<= ...... ;
`F2 : if( ACK==1 ) STATE<= ...... ;
`F3 : STATE<= ...... ;
`DEC :
begin
case ( `OP_4 ) // Decode for 4-bit opecode
`IR_LDD : STATE<=`LDD_1;
`IR_STD : STATE<=`STD_1;
`IR_CALL : STATE<=`CALL_1;
`IR_JP, ... , ... , ... , ...
: ... ;
default :
case ( `OP_6 ) // Decode for 6-bit opecode
`IR_ADD, `IR_SUB, `IR_OR, `IR_EOR, `IR_AND
: if( `OP_M==`IMM ) STATE<=`BIOP_IMM_1; else
if( `OP_M==`IDX ) STATE<=`BIOP_IDX_1; else
STATE<=`F1; // Undefined instruction
`IR_INC, `IR_DEC, `IR_MV
: ...... ;
`IR_NOT, `IR_LSL, `IR_ASL, `IR_LSR,
`IR_ASR, `IR_ROL, `IR_ROR, `IR_SWP
: ...... ;
`IR_LD : if( ... ) ...... ; else
if( ... ) ...... ; else
...... ;
`IR_ST : if( ... ) ...... ; else
...... ;
`IR_IN : ...... ;
`IR_OUT : ...... ;
`IR_POP : ...... ;
`IR_PUSH : ...... ;
`IR_RET : ...... ;
`IR_HALT : ...... ;
`IR_NOP : ...... ;
default : STATE<=`F1; // Undefined instruction
endcase
endcase
end
//
// LD Imm
//
`LDI_1 : STATE<=`F1;
//
// LD Index
//
`LDX_1 : STATE<=`LDX_2;
`LDX_2 : if( ACK==1 ) STATE<=`LDX_3;
`LDX_3 : STATE<=`F1;
//
// LD Direct
//
`LDD_1 : STATE<=`LDD_2;
`LDD_2 : if( ACK==1 ) STATE<=`LDD_3;
`LDD_3 : STATE<=`F1;
//
// ST Index
//
`STX_1 : ...... ;
`STX_2 : ...... ;
`STX_3 : if( ACK==1 ) ...... ;
`STX_4: ...... ;
//
// ST Direct
//
`STD_1 : ...... ;
`STD_2 : ...... ;
`STD_3 : if( ACK==1 ) ...... ;
`STD_4 : ...... ;
//
// CALL
//
`CALL_1: ...... ;
`CALL_2: ...... ;
`CALL_3: if( ACK==1 ) ...... ;
`CALL_4: ...... ;
`CALL_5: ...... ;
//
// Branch Instructions
//
`JP_1 : ...... ;
//
// Binary Instructions
// ADD, SUB, OR, EOR, AND
`BIOP_IMM_1 : ...... ;
//
// BIOP Index
// ADD, SUB, OR, EOR, AND
`BIOP_IDX_1 : ...... ;
`BIOP_IDX_2 : if( ACK==1 ) ...... ;
`BIOP_IDX_3 : ...... ;
//
// INC & DEC & MV
//
`INC_DEC_MV : ...... ;
// Mono operand instructions
// NOT and all shift instructions
`MONO_1 : ...... ;
//
// INPUT instruction
//
`IN_1 : ...... ;
`IN_2 : if( ACK==1 ) ...... ;
`IN_3 : ...... ;
//
// OUTPUT instruction
//
`OUT_1 : ...... ;
`OUT_2 : ...... ;
`OUT_3 : if( ACK==1 ) ...... ;
`OUT_4 : ...... ;
//
// POP
//
`POP_1 : ...... ;
`POP_2 : if( ACK==1 ) ...... ;
`POP_3 : ...... ;
//
// PUSH
//
`PUSH_1 : ...... ;
`PUSH_2 : ...... ;
`PUSH_3 : if( ACK==1 ) ...... ;
`PUSH_4 : ...... ;
//
//
//
`RET_1 : ...... ;
`RET_2 : if( ACK==1 ) ...... ;
`RET_3 : ...... ;
//
// HALT
//
`HALT_1 : STATE <= `HALTING;
//
// NOP
//
`NOP_1 : STATE <= `F1;
default : STATE <= `F1; // Undefined instruction
endcase
end
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