The description of the decoder
As the show by the previous example, the description of the decoder can be described in the part which hits State of the decoding in case of state transition.
However, in some cases, it sometimes had better describe separately as the combination circuit, too.
Hereinafter, SIGN which is the control signal which decides whether it makes all values of 8 bits of higher ranks 0 when reading a 8-bit value from BRANCH which is the control signal which decides whether or not to branch or whether or not not to do "YO" sea urchin and the control-register or whether or not it makes them 1 and so on are the example.
reg BRANCH ; // Branch TRUE for decode
reg SIGN ; // Sign Extention mode for decode
//------------------------------------------------------------------//
// BRANCH flag and SIGN flag are made from IR and FR
//------------------------------------------------------------------//
always @ (IR or FR)
begin
BRANCH<= 1'bx;
SIGN <= 1'bx;
case ( `OP_4 )
`IR_JP : BRANCH<=1;
`IR_JPS : BRANCH<=FR[3];
`IR_JPZ : BRANCH<= ...
`IR_JPV : BRANCH<= ...
`IR_JPC : BRANCH<= ...
default :
case ( `OP_6 )
`IR_ADD : SIGN<=IR[7];
`IR_SUB : ...
`IR_OR : if ( `OP_M==`IMM ) SIGN<=0; else SIGN<=IR[7];
`IR_EOR : ...
`IR_AND : ...
`IR_LD : ...
`IR_ST : ...
endcase
endcase
end
The way of thinking
- BRANCH : It becomes "1" only when branch true about five kinds of branch instructions.
When generating the control
signal of the branch instruction in case of control signal generation
to design later, it is possible to generate easily in referring to this
BRANCH signal.
- SIGN : It uses whether or not it makes all values of 8 bits of higher
ranks 0 when reading a 8-bit value from the control-register or whether
or not it makes them 1 as the control signal to fix. This control
depends on the kind and the addressing mode of the direction. Be
careful of the following and create.
- Indexed addressing : The value to output in this case
from the instruction register becomes a sign-extension certainly. Because
it makes all values of 8 bits of higher ranks "0"; in case of
the positive value, in case of the value of 0 extended.
the negative, it becomes "1" piece of extension; because it makes all
values of 8 bits of higher ranks "1".
- Immediate addressing : the value to output from the
control-register becomes an operand just as it is but differs in the
value to output as 8 bits of higher ranks by the direction.
In ADD and SUB instructions, 8-bit value is sign-extended to 16-bit value.
Also, each logical operation of Boolean ADD, AND and the exclusive OR is
"0 pieces of extension" or "1 piece of extension" as
8 bits of higher ranks of the accumulator are left just as it is. In the
LD immediate value, it makes 8 bits of all higher ranks "0".
Next, description of control signal generation attempts to have.
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