There are synchronous reset and asynchronous reset in the reset. Which of the synchronous reset and the asynchronous reset to choose can not declare purpose about the design philosophy sweepingly when which is better. It says that it makes the reset (it sometimes says super reset, too,) of the system-wide asynchronous reset generally like an environment operating of the digital-system. Also, this time, it makes FPGA of the Xilinx Inc. an implementing object device but at this device, the circuit becomes smaller in the one which used asynchronous reset. Therefore, this time, it uses asynchronous reset.
In the KITE microprocessor, it always outputs the contents of the register inside the processor beforehand out of the chip and it is made to be able to be observed. Therefore, the accumulator, the stack pointer, the index register, each register of the program counter prepare beforehand the output terminal which always outputs contents beforehand. (The operation of the processor doesn't have direct relationship.) The control-register, the flag-register and the address register must always output a value beforehand but for the observation, they are using this output.
The description of the register consult the following.
module acc ( I, T, the O, CLK, RST, W, R) ;
input [15:0] I ;
output [15:0] T ;
output [15:0] O ;
input CLK ;
input RST ;
input W ;
input R ;
reg [15:0] tmp ; // for Register
always @ (posedge RST or posedge CLK)
begin
if (RST == 1'b1)
tmp<= ...
else if ( W == 1'b1 )
tmp <= ...
end
assign O = ... ;
assign T = ( ... ) ? ... : ... ;
endmodule
It is a 12-bit register but because the internal bus is 16 bits, it
makes input/output to the bus 16 bits. In output, in addition to 12
bits of the register, it makes 4 bits of higher ranks "0000"
beforehand.
Because the description is the same as the index register completely about the stack pointer, it is adequate if only one file, too, gets ready.
module r12 ( I, T, the O, CLK, RST, W, R) ;
input [11:0] I ;
output [15:0] T ;
output [11:0] O ;
input CLK ;
input RST ;
input W ;
input R ;
reg [11:0] tmp ; // for Register
always @ (posedge RST or posedge CLK)
begin
if (RST == 1)
tmp<= ... ;
else if ( W == 1 )
tmp <= ... ;
end
assign O = ... ;
assign T = ( ... ) ? ... : ... ;
endmodule
It is a 12-bit register but because the internal bus is 16 bits, it makes input/output to the bus 16 bits. In output, in addition to 12 bits of the register, it makes 4 bits of higher ranks "0000" beforehand. The feature to do a program counter in +1 to do the following direction in the fetch must be included beforehand.
module pc ( I, T, the O, CLK, RST, W, R, P) ;
input [11:0] I ;
output [15:0] T ;
output [11:0] O ;
input CLK ;
input RST ;
input W ;
input R ;
input P ;
reg [11:0] tmp ; // for Register
always @ (posedge RST or posedge CLK)
begin
if (RST == 1)
tmp<= ... ;
else if ( W == 1 )
tmp <= ... ;
else if ( P == 1 )
tmp <= ... ;
end
assign O = ... ;
assign T = ( ... ) ? ... : ... ;
endmodule
As for the contents of the register, there is a continuous output beforehand. In the writing in to the register, it is necessary to make rewrite from two in case of 3 bus-arrangements buses beforehand. It treats a reset signal from outside as the set signal. In other words, in reset, all contents of the register make "1" become.
module ar (I1, I2, the O, CLK, SET, W1, W2) ;
input [11:0] I1 ;
input [11:0] I2 ;
output [11:0] O ;
input CLK ;
input SET ;
input W1 ;
input W2 ;
reg [11:0] tmp ; // for Register
always @ (posedge SET or posedge CLK)
begin
if (SET == 1)
tmp<= ... ;
else if ( W1 == 1 )
tmp <= ... ;
else if ( W2 == 1 )
tmp <= ... ;
end
assign O = ... ;
endmodule
As for the contents of the register, there is a continuous output beforehand.
module fr ( I, the O, CLK, RST, W) ;
input [3:0] I ;
output [3:0] O ;
input CLK ;
input RST ;
input W ;
reg [3:0] tmp ; // for Register
always @ (posedge RST or posedge CLK)
begin
if (RST == 1'b1)
tmp<= ... ;
else if ( W == 1'b1 )
tmp <= ... ;
end
assign O = ... ;
endmodule
There are two pieces of output to the continuous output and the bus in the contents of the register. Moreover, the output to the bus has the way of two pieces of output respectively.
//
// Instruction Register
//
module ir (I, T1, T2, the O, CLK, RST, W, R12, R8P1, R8P2, R8M2) ;
input [15:0] I ;
output [15:0] T1 ;
output [15:0] T2 ;
output [15:0] O ;
input CLK ;
input RST ;
input W ;
input R12, R8P1, R8P2, R8M2 ;
reg [15:0] tmp ; // for Register
reg [15:0] ..., ...; // The declaration which is necessary at the combination circuit by always
always @ (posedge RST or posedge CLK)
begin
if ( RST == 1'b1 ) tmp<= ... ; else
if ( W == 1'b1 ) tmp <= ... ;
end
assign O = ... ;
//
// Output Control for 1st DATA Bus
//
always @( tmp or R12 or R8P1 )
begin
if ( R12 == 1'b1 ) ... <= ... ; else
if ( R8P1 == 1'b1 ) ... <= ... ; else
... <= ... ;
end
//
// Output Control for 2nd DATA Bus
//
always @( tmp or R8P2 or R8M2 )
begin
if ( R8P2 == 1'b1 ) ... <= ... ; else
if ( R8M2 == 1'b1 ) ... <= ... ; else
... <= ... ;
end
endmodule
Because the composition is simple, the register thinks that it makes a mistake never first.
To this place when advancing towards design of decoder sequencer in simulation,
skipping
To this place when checking that register works by simulation