Creating of a testbench for ALU

To simulate ALU, a testbench must be created. It saves the following text in the file name, "alu_test".

Note that you must check enumerated arguments of dot notation.

`timescale 1ns/1ns
`include "alu_op.v"

module alu_test ;
  reg   [15:0] A;	// input is defined as reg type
  reg   [15:0] B;
  reg   [ 3:0] CB;
  wire  [15:0] Y;	// output is defined as wire type
  wire  [ 3:0] F;

  wire S, Z, V, C ;

  initial		// Record signal changes for wave viewer
  begin
     $shm_open("waves.shm");
     $shm_probe("as");
  end

  `include "alu_test.vct" // test vector

  alu U1 ( .A(A), .B(B), .CB(CB), .Y(Y), .F(F) ); // Instanciation for Design Under Test, DUT

  assign S = F [3];
  assign Z = F [2];
  assign V = F [1];
  assign C = F [0];

endmodule

Next, Creating of a test vector

|Home|

Last modified on