Creating of a test vector

The test vector must be described in "alu_test.vct" in Verilog HDL.
This file automatically generated from vector script "alu_test.txt" by hand-made "make_vector.pl" command.

After saving the following file as "alu_test.txt".

# input
A [15:0]
B [15:0]
CB [3:0]

# testvector
#     A [15:0]    B [15:0]    CB [3:0]
100 16'h0001 16'h0001 `IADD               # add
100 16'h0001 16'hFFFF `IADD
100 16'hFFFF 16'h0001 `IADD
100 16'h8000 16'h8000 `IADD
100 16'h7FFF 16'h0001 `IADD
100 16'h0001 16'hFFFE `IADD
100 16'hFFFE 16'h0001 `IADD
100 16'hFFFF 16'hFFFF `IADD

Execute following command.

% make_vector alu_test.txt > alu_test.vct

It generates the test vector file in Verilog HDL.
Generated "alu_test.vct" is as follows.

initial
begin
    A [15:0]=# 100 16'h0001 ;     //    add
    A [15:0]=# 100 16'h0001 ;
    A [15:0]=# 100 16'hFFFF ;
    A [15:0]=# 100 16'h8000 ;
    A [15:0]=# 100 16'h7FFF ;
    A [15:0]=# 100 16'h0001 ;
    A [15:0]=# 100 16'hFFFE ;
    A [15:0]=# 100 16'hFFFF ;
end

initial
begin
    B [15:0]=# 100 16'h0001 ;     //    add
    B [15:0]=# 100 16'hFFFF ;
    ...

This "alu_test.vct" is included from "alu_test.v".

Next, Functional simulation.

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