Functional simulation

Here, three files of "alu_test.v", "alu.v" and "alu_op.v" could be prepared.
It does a simulation using these three files.
It uses verilog command as follows. Note that "alu_op.v" is not require in argument list because of automatically including from "alu.v". 
% verilog alu_test.v alu.v
Then, a message is output as follows and the simulation ends.
If error occurrs, please check the source code. 
verilog alu_test.v alu.v
VERILOG-XL March 3rd, 2     18:43:29, April 22nd, 1998

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Compiling source file "alu_test.v"
Compiling included source file "alu_op.v"
Continuing compilation of source file "alu_test.v"
Compiling source file "alu.v"
Compiling included source file "alu_op.v"
Continuing compilation of source file "alu.v"
Highest level modules :
alu_test

0 simulation events (use + profile or + listcounts option to count)
CPU time : 0.1 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of VERILOG-XL March 3rd, 2     18:43:44, April 22nd, 1998
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