Test program "testadd.asm"
In this program, it creates a listing file using kiteasm.
% kiteasm-l testadd
000001 ; 000002 ; The addition program which used a recursion 000003 ; 000004 ; lab. mnemonic comment 000005 .text 000006 0000 C108 _MAIN : ld #0x8 000007 0001 B.C. 00 swp 000008 0002 9100 or #0x00 ; sp=0x800 000009 0003 F004 mv sp, acc 000010 0004 C800 in 0 ; input n 000011 0005 D400 push 000012 0006 200A call radd 000013 0007 D000 pop 000014 0008 CC00 out ; result 000015 0009 F800 halt 000016 ; 000017 000A F009 radd : mv ixr, sp 000018 000B C201 ld ixr, 1 000019 000C D400 push 000020 000 D 9100 or #0 000021 000E 5015 jpz radd0 000022 000 F 8C00 dec acc 000023 0010 D400 push 000024 0011 200A call radd 000025 0012 D000 pop 000026 0013 F009 mv ixr, sp 000027 0014 8200 add ixr, 0 000028 0015 F009 radd0 : mv ixr, sp 000029 0016 C602 st ixr, 2 000030 0017 D000 pop ; dummy pop 000031 0018 E000 ret 000032 000033 .data 0x100 000034 0100 0000 ZERO : .word 0 000035 0101 0064 D100 : .word 100 000036 000037 .const 0xfff 000038 0FFF 0000 .word _MAIN
The % lst2ram testadd.lst
@0000 C108 // 000006 0000 C108 _MAIN : ld #0x8 @0001 B.C. 00 // 000007 0001 B.C. 00 swp @0002 9100 // 000008 0002 9100 or #0x00 ; sp=0x800 @0003 F004 // 000009 0003 F004 mv sp, acc @0004 C800 // 000010 0004 C800 in 0 ; input n The omission @0101 0064 // 000035 0101 0064 D100 : .word 100 @0fff 0000 // 000038 0FFF 0000 .word _MAIN
$readmemh ("testadd.ram", MEM) ;
It is described as it is.
The value also, which types in when executing IN direction
io_DATA=000 a of 16'h ; // Input Value
When doing a simulation, all files except the one which is referred to in include in the Verilog-HDL description which was written so far must be written. Ex. )
The % verilog kite_test.v kite_top.v kite.v alu.v acc.v ir.v r12.v pc.v fr.v ar.v dec_seq.vIf or, for example save a typing in argument part beforehand in the file like "kite.vv"
% verilog-f kite.vvIt is possible to execute being.
In the simulation by this file, it stops a simulation by executing HALT direction. Therefore, the simulation doesn't stop at the KITE processor during debugging not to execute HALT direction. In the case, it is ^C key After pressing (control C) and stopping a simulation, get out of a simulator with the ^D key.
It becomes following result when doing a simulation by above method.
The corrugated output screen is as follows.
The red cursor spot is changing 1.106 milliseconds later (it is behind 1106 clock because it is using a 1-MHz clock) from the fruit line-start and the HALT signal is changing into "H" from "L".
By this, it shows that the simulation stopped with the HALT direction.
Also, the value of the accumulator shows "0037" but this means 55 hexadecimal numbers which are 1-10 addition results.
It shows that the designed processor executed this program correctly in this way.
Even if "testadd.asm" moves, the KITE-1 processor isn't complete.
Because, this program is KITE-1 It is because it is using only the part of the direction of the processor.
Let's attempt to make execute following program (perfect.asm) about whether or not the operation of the processor is right.
This program becomes the test program that it used all directions of the KITE-1 microprocessor and to have considered whether or not the operation of the direction was right that it was possible to check.
The example of perfect.asm is shown below.
The value of the accumulator near the 5739000-ns time shows "900D" and gets off.
It is possible to confirm that it is working right approximately.
It is of the difficult skill that, when the circuit has a bug, it finds out that which direction is right, whether or not you work and which direction doesn't work right only by the corrugated display. Therefore, next, it introduces the method of simulation by expectation value comparison.
My mail address iskuga@cs.kumamoto-u.ac.jp
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