Logic Simulation with Verilog-XL

The simulation by the expectation value comparison

In the previous example, it displayed the corrugation of the execution result, executing a program by the assembler. However, in this case, finding the one which where has a mistake is a difficult skill. Therefore, this time, it introduces about the way of comparing the expectation value of the simulation result, saying the output by the simulator.

It is KITE in "testadd.hex" which is a fruit line image after assembly of "testadd.asm" Following information can be gotten when hanging on the simulator ("kitesim").

% kitesim testadd.hex

Start address=000
  ---- acc=0000 ixr=000 sp=000 out=0000 pc=000       c108 ld        #0x08
  ---- acc=0008 ixr=000 sp=000 out=0000 pc=001       bc00 swp
  ---- acc=0800 ixr=000 sp=000 out=0000 pc=002       9100 or        #0x00
  ---- acc=0800 ixr=000 sp=000 out=0000 pc=003       f004 mv      sp, acc
  ---- acc=0800 ixr=000 sp=800 out=0000 pc=004       c800 In        0x00
The omission
  ---- acc=0037 ixr=7fd sp=800 out=0000 pc=008       cc00 out       0x00
  ---- acc=0037 ixr=7fd sp=800 out=0037 pc=009       f800 halt
  ---- acc=0037 ixr=7fd sp=800 out=0037 pc=00a     f009 mv      ixr, sp

This means the trace of the direction execution. That is, this direction execution trace is the meaning which becomes the execution expectation value when simulating the processor which you created. If the logic simulator can output an execution result with the format which is the same as this expectation value, it is possible to compare in the agreement at a breath by the "diff" command of the UNIX.

It is described in the description of "kite_test.v" for the execution result to be able to be output with the format which is the same as this expectation value. When doing a simulation, following log is output in "verilog.log" which is log at the time of the simulation.

The omission
  ---- acc=0008 ixr=000 sp=000 out=0000 pc=001       bc00
  ---- acc=0800 ixr=000 sp=000 out=0000 pc=002       9100
  ---- acc=0800 ixr=000 sp=000 out=0000 pc=003       f004
The omission
  ---- acc=0037 ixr=7fd sp=800 out=0037 pc=009       f800
  ---- acc=0037 ixr=7fd sp=800 out=0037 pc=00a     f009
The omission

To understand if seeing than outputting KITE simulator, the output of the KITE simulator shows that it is output with the format which omitted an assembly description.

Therefore, it prepares a file in the part which omitted an assembly description from the output of the KITE simulator as the expectation value file, and also it copies only the part to support the expectation value from the "verilog.log" file and it makes beforehand it one file. Later, it compares these two files only.

It is possible if saving output to the screen to the file using the redirection to create the file of the expectation value.

% kitesim testadd.hex > testadd.sim

It makes an unnecessary part (Nimonic and so on) the removal expectation value file from this "testadd.sim" file.
When deleting a disused part, it is possible to delete easily when using delete-rectangle (the rectangular area deletion) of emacs.

It brings the character in the upper left in the rectangular area to want to delete a cursor.
It set-marks in Ctrl+SPACE.
It brings the character in the lower right in the rectangular area to want to delete a cursor.
Ctrl+x It delete-rectangles in r d.

The execution result of the "diff" command when picking out the file name of the expectation value from "testadd.sim", picking out the execution trace-information of the logic simulator from the "verilog.log" file and saving it as "simout.tmp"

[panther] [1414]% of 4 bits of diff testadd.sim simout.tmp
[panther] ~/work/cadence/ of [1413]% of 4 bits of
~/work/cadence/

If there is not a part which is this different from the file, nothing outputs a message. It is possible to confirm that the processor which was designed in this case is working as the expectation value.

Above, the description of the KITE-1 microprocessor is completion.

Next, IP of the KITE microprocessor.

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