The KITE-1 Microprocessor Design (Multiplexer Version)

The design of multiplexer version of the KITE-1 microprocessor

As for former practice, in the design of the KITE microprocessor, it designed a tri state buffer, making a use internal bus by tristate. Because the internal bus composition of the processor could be specifically designed, this had the merit for which it is easy to understand the composition of the processor.
However, generally, it doesn't use tristate bus from the following reason.

Generally, the operation of the tri state buffer is low-speed.
There is a way of realizing tristate bus just as it is, too, in the design method which connects an existence IP as the block in the integrated circuit. However, there is not using tristate bus generally as the internal bus about the gate array ordinarily.

Therefore, first, it begins because it changes KITE processor into multiplexer-type structure.
It consults the following bus-arrangement figure and it makes the bus of the KITE microprocessor a multiplexer.

The change from tristate bus :

The register : As for each register of the accumulator, IXR, SP, the PC, there is a description in the tri state buffer, but it deletes a part about this and the continuous output has the value of the register beforehand in it. As for the IR, it deletes a description in the tri state buffer but it does each output of R12, R8P1, R8P2, R8M2 in the continuous output. Also, there is a continuous output beforehand about value itself of the IR register, too, as the output to the decoder.

Also, an original AR register is designed to be preset by the reset input. This is to read the address of address 0xFFF as the start vector as the vector start after reset. However, arrange the vector table of KITE-2 and to adjust, it changes a start vector into 0x000. Specifically, it makes reset (it is initialized to 0) a register with the reset signal.
The description change by the kite.v hierarchy : Because it excluded a description in the tri state buffer from the register, the port of the reading control signal and the tri state computer output signal from the register passes away. It changes as the port list in case of the instance summon agrees in kite.v which is a higher rank hierarchy.
The description of the multiplexer about the kite.v hierarchy : Three multiplexers must be created as shown in the configuration example.
- The multiplexer of the ALU Sanyuu power : R12 from the control-register and either of the entries (DATAI) from the PC SP IXR the accumulator R8P1 outside the processor are made to be able to be chosen. These choices use the control signals IR_R12, IR_R8P1, ACC_R, IXR_R, SP_R, PC_R, DBI1 which are output from the decoder sequencer unit.
- The multiplexer of the ALU right entry : R8P2 from the control-register, and R8M2, either of the entries (DATAI) from outside the processor are made to be able to be chosen. These choices use the control signals IR_R8P2, IR_R8M2, DBI2 which are output from the decoder sequencer unit.
- The multiplexer for the data-output : It chooses the value of the accumulator or the PC. These choices use the control signals ACC_R, PC_R which are output from the decoder sequencer unit.
The change of the input/output about the kite.v hierarchy : In KITE of the tri state version, a data bus was defined as follows.
```
module kite( DATA1,                       // 1st DATA Bus
             DATA2,                       // 2st DATA Bus

  inout  [15:0] DATA1,                    // 1st DATA Bus
                DATA2;                    // 2nd DATA Bus
```
kite.v became the hierarchy which is equivalent to the module when handling a processor as the soft core, but the 1st data bus and the 2nd data bus were separated and moreover was set to the bi-directional-bus.
To make it be easy to use as the soft core IP, it separates a data bus as follows at the bus (DATAI) for the entry and the bus (DATAO) for the output. It changes the part which influences with change of the variable name.
```
module kite( DATAI,                       // DATA Bus for Input
             DATAO,                       // DATA Bus for Output

  input  [15:0] DATAI;                    // in  DATA Bus
  output [15:0] DATAO;                    // out DATA Bus
```
The change of the AR_W2 control signal at the decoder sequencer:
In the configuration example, only the SP register can write in as the writing in (AR_W2) of the AR register from the upper side. As the writing in from AR_W2 by KITE of the tri state version
- The PC→AR transfer in instruction-fetch F1 State
- The IR_R12→AR transfer in direct addressing direction E1 State
- The IR_R8P1→AR transfer in IN/OUT direction E1 State
- The SP→AR transfer in POP/RET direction E1 State
Among these, it is possible to be realized in writing from AR_W1 making via ALU except the SP→AR transfer. Therefore, in this configuration example, only the SP register made support as the writing in by AR_W2.
The change-point about the kite_top.v hierarchy : Because it changed the variable declaration of the kite.v hierarchy, it makes alterations in the style to support this.
Of the description below about the buffer control of both directions of the multiplexer version
```
  //
  // Bidirectional Buffer and controls
  //
  assign DATA1 = (DBI1)? DATA  : 16'hZZZZ ;
  assign DATA2 = (DBI2)? DATA  : 16'hZZZZ ;
  assign DATA  = (RW  )? DATA1 : 16'hZZZZ ;
```
It changes as follows. It changes the part which accompanies DATAI, DATAO of course, too.
```
  //
  // Bidirectional Buffer and controls
  //
  assign DATAI=DATA ;
  assign DATA = (RW)? DATAO : 16'hZZZZ ;
```

In above change, it is possible to change into the multiplexer version from the tri state buffer version. It debugs until it works with no problem using perfect.asm which is a test program.

Next, embedded system with the KITE microprocessor IP.

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