Logic synthesis and layout on FPGA

FPGAへの実装処理を行います。 Verilog HDLによる8ビットALUのシミュレーションが終了した後、
論理合成・配置・配線といったFPGAへの実装処理を行います。

実装処理を行うには、Xilinx社製設計ツールである ISE を使用します。
Enter 
ise &
to execute the design tool.

Make a new project as "alu".


Push "Next".
In next "Project Settings" window, select a target FPGA device.

Set following 4 fields;

  1. Family: Artix7
  2. Device: XC7A100T
  3. Package: CSG324
  4. Speed: -1
and push "Next".
In next window, push "Finish".
In these steps, the project is generated for ALU implementation.

Next, you register 3 files into the prtoject.

In next window, you confirm no error in registered files, and push "OK".

You select "alu (alu.v)" from "Hierarchy" window, and you execute "Generate Programming File" by right click of mouse in "Process: alu" window.



After implementation process, you confierm that "Errors:" field indicates "No Errors" in "Implementation Status:" window.
And also, you confirm that "Process "Generate Programming File" completed successfully" in "Console" window.



And then you confirm a log in "Pinout Report".
Like a below figure, it is no problem that "IO Standard" field indicates "LVCMOS33".
However, you must re-execute the implementation process except "LVCMOS33" cases.
To re-execute the implementation process, you execute "Rerun All" by right click of mouse at "Generate Programming File" in "Process" window.
After implementation process, you reconfirm that "IO Standard" field indicates "LVCMOS33".



Is There no problem in implementation process?
Next, post-layout simulation with real wire delay .

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