Implementation for 8-bit ALU

Implementation process for NEXYS4 board

We have to implement the design to an FPGA so that the designed ALU will behave on an FPGA.
We use a circuit board, NEXYS4 by Digilent.

For implementation, we have to write a design constraint file "alu.xdc".
Some constraints are described in xdc file.

"PACKAGE_PIN" indicates to assign the input or output variable to the physical FPGA pin.
"IOSTANDARD VLCMOS33" indicates to set the FPGA pin for Low Voltage CMOS 3.3V.
"CONFIG_VOLTAGE" and "CFGVBS" indicate configuration settings for the NEXYS4 board.

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGVBS GND [current_design]

## Switches
set_property PACKAGE_PIN U9 [get_ports {B[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[0]}]
set_property PACKAGE_PIN U8 [get_ports {B[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[1]}]
set_property PACKAGE_PIN R7 [get_ports {B[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[2]}]
set_property PACKAGE_PIN R6 [get_ports {B[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[3]}]
set_property PACKAGE_PIN R5 [get_ports {B[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[4]}]
set_property PACKAGE_PIN V7 [get_ports {B[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[5]}]
set_property PACKAGE_PIN V6 [get_ports {B[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[6]}]
set_property PACKAGE_PIN V5 [get_ports {B[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {B[7]}]

set_property PACKAGE_PIN U4 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
set_property PACKAGE_PIN V2 [get_ports {A[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
set_property PACKAGE_PIN U2 [get_ports {A[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[2]}]
set_property PACKAGE_PIN T3 [get_ports {A[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[3]}]
set_property PACKAGE_PIN T1 [get_ports {A[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[4]}]
set_property PACKAGE_PIN R3 [get_ports {A[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[5]}]
set_property PACKAGE_PIN P3 [get_ports {A[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[6]}]
set_property PACKAGE_PIN P4 [get_ports {A[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[7]}]

## LEDs
set_property PACKAGE_PIN T8 [get_ports {Y[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[0]}]
set_property PACKAGE_PIN V9 [get_ports {Y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[1]}]
set_property PACKAGE_PIN R8 [get_ports {Y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[2]}]
set_property PACKAGE_PIN T6 [get_ports {Y[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[3]}]
set_property PACKAGE_PIN T5 [get_ports {Y[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[4]}]
set_property PACKAGE_PIN T4 [get_ports {Y[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[5]}]
set_property PACKAGE_PIN U7 [get_ports {Y[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[6]}]
set_property PACKAGE_PIN U6 [get_ports {Y[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[7]}]

set_property PACKAGE_PIN P5 [get_ports {F[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {F[0]}]
set_property PACKAGE_PIN U1 [get_ports {F[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {F[1]}]
set_property PACKAGE_PIN R2 [get_ports {F[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {F[2]}]
set_property PACKAGE_PIN P2 [get_ports {F[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {F[3]}]

##Buttons
set_property PACKAGE_PIN T16 [get_ports {CB[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CB[2]}]

set_property PACKAGE_PIN E16 [get_ports {CB[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CB[1]}]

set_property PACKAGE_PIN R10 [get_ports {CB[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CB[0]}]

Next, logic systhesis and layout on FPGA .

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