Memory Module Design

The creating of a memory module

It creates the memory module which becomes the main memory of the KITE processor.

It summons a memory module as follows from the kite_top hierarchy.

  //
  // Memory and Video RAM
  //
  memory mem0 ( .CLK (CLK75)
                ADDR (The ADR)
                DATAI (DATAO)
                DATAO (MEM_DATAO)
                MREQ (MREQ)
                RW (RW)
                ACK (MEM_ACK)
              ) ;

Therefore, the input/output of the memory module is as follows.

module memory (CLK, ADDR, DATAI, DATAO, MREQ, RW, ACK) ;
  input     
  output  

  

endmodule

The main memory prepares 2-K Word at the 16-bit width.
It declares a memory as the arrangement.

        reg     [15:0] MEM [0:2047] ;

As for the memory writing in operation, it is described using always, but is the memory implemented as the internal-block memory of FPGA by the difference of the form or is implemented as the group of FF and is different. The form depends on the logic appulse software to use, too.

ISE which is made by the Xilinx Inc. to use this time can implement as the internal-memory when described as follows.

The way of thinking :

The writing in to the memory makes write DATAI of the outside data in the place of the concerned address of the memory by the clock synchronization at the time of "the MREQ signal is valid", "the RW signal writes notes" and moreover "the result of the address decoding by the memory is valid".
```
  always @ (posedge CLK)
  begin
    if (MREQ ==    ... && RW == ... && ADDR [...] == .....      )
       MEM [ADDR [... : ...]]<= DATAI;
  end
```
Because Jules becomes the memory of Word in 2 K of the first halves in Word of KITE in 4 K of memory space, as for the address decoder, this memory, too, will should decode only a high-order bit in 12 bits of ADDR.
The reading from the memory is OK if substituting the contents of the concerned address to read for DATAO in assign.

In case of FPGA which is made by the Xilinx Inc., it is possible to be realized as the dual port memory which used internal-block RAM in above mentioned description.
As for the acknowledge signal (ACK), it reads and writes to this memory module. It makes return as value 1 when putting-on is done.
It makes return ACK when the address decoding signal and the MREQ signal are valid.

The initialization of the memory by the program to execute :

The program to execute with the KITE processor is realized in loading the binary image (the machine instruction) of the program on the memory.

$readmemh() in case of Verilog HDL can be initialized in using and the contents of the memory can be beforehand initialized by the program of KITE.
When initialized by the contents of the kite.ram file to the MEM arrangement to have secured the memory, it is described as follows.

   initial
   begin
      $readmemh("kite.ram", MEM) ;
   end

It makes a file for the memory initialization the file format which it is possible to use for $readmemh using the lst2ram command after creating .lst file using kite_asm.
Incidentally, because the specification of $readmemh depends on the Verilog-XL simulator and the Xilinx ISE logic synthesis, it makes not leave an option as follows in the "lst2ram" command.

kiteasm xxxx.asm
lst2ram -s -f -2 xxxx.lst

※ As for the LIFE game program to create this time, it is explained in the after page. The .ram file which was created by the above command can be used at both of the Verilog XL simulator and the Xilinx ISE logic synthesis.

Next, it creates CUI module.

| Back |