24 bits in amount of 8 bits of RGBs for each which are output every 75 MHz must be output as the high-speed serial signal with the DVI form which is a digital video signal.
It uses a DVI encoder module for the case.
This time, it is provided as the reference design of ATLYS which is an experiment board.
It uses dvi_out_native module just as it is.
The dvi_out_native module-construction becomes like the following figure.
Also, the actuation is as the following.
It encodes the parallel signal of 8 bits for each of RBG to 10 bits according to the rule of the DVI signal with the encoder module.
It replaces 10 bits for each of the gotten RGB with 5 bits of the epistasis hypostasis every boiling row and it makes a 30-bit signal.
It sends a 30-bit signal every 15 bits at twice of cycleses per minute with the convert_30_to_15 module.
It changes 5 bits for each of the RGB with the parallel-the serial at 10 times of cycleses per minute with the serdes_n_to_1 module and it sends them.
It outputs as the differential-signal of LVDS by the OBUFDS primitive.
It creates a clock for the DVI separately and it outputs it with the serial signal of the RGB.
Because the association file of dvi_out_native gets ready beforehand, it is the following command.
It copies a boiling strand and it adds all files to the project.
To make former alteration valid, it is the one of the menu. "Project"-> "Rescan User
Repositories"
It executes "WO" beforehand.
Next, it is installation of VGA controller IP and DVI encoder module.
The bibliography
Urushidani justice : "The Chapter 5 image input and display corollary bass/interface specification ," Interface September, 2009 number, pp.76-84, the CQ Publishing Co. Inc.
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